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DS2152 Enhanced T1 Single-Chip Transceiver
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FEATURES
Complete DS1/ISDN-PRI transceiver functionality Line interface can handle both long and short haul trunks 32-bit or 128-bit crystal-less jitter attenuator Generates DSX-1 and CSU line build outs Frames to D4, ESF, and SLC-96R formats Dual onboard two-frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.192 MHz 8-bit parallel control port that can be used directly on either multiplexed or non-multiplexed buses (Intel or Motorola) Extracts and inserts robbed-bit signaling Detects and generates yellow (RAI) and blue (AIS) alarms Programmable output clocks for Fractional T1 Fully independent transmit and receive functionality Integral HDLC controller with 16-byte buffers for the FDL Generates and detects in-band loop codes from 1 to 8 bits in length including CSU loop codes Contains ANSI 1's density monitor and enforcer Large path and line error counters including BPV, CV, CRC6, and framing bit errors Pin compatible with DS2154 E1 Enhanced SingleChip Transceiver 5V supply; low power CMOS 100-pin 14mm2 body LQFP package
PIN ASSIGNMENT
100 1
ORDERING INFORMATION
DS2152L DS2152LN (0C to 70C) (-40C to +85C)
DESCRIPTION
The DS2152 T1 Enhanced Single-Chip Transceiver contains all of the necessary functions for connection to T1 lines, whether they be DS-1 long haul or DSX-1 short haul. The clock recovery circuitry automatically adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both DSX-1 line build outs as well as CSU line build outs of -7.5 dB, -15 dB, and -22.5 dB. The onboard jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set of internal registers which the user can access and control the operation of the unit. Quick access via the parallel control port allows a single controller to handle many T1 lines. The device fully meets all of the latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (12-90), AT&T TR54016, and ITU G.703, G.704, G.706, G.823, and I.431. 1 of 94 092299
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TABLE OF CONTENTS 1.0 INTRODUCTION ..................................................................................... 4
Block Diagram............................................................................................................................... Pin List........................................................................................................................................... Pin Description .............................................................................................................................. Register Map.................................................................................................................................. 6 7 9 13
2.0 3.0
PARALLEL PORT................................................................................... 17 CONTROL, ID, AND TEST REGISTERS ................................................ 18
Payload Loopback ......................................................................................................................... Framer Loopback........................................................................................................................... Pulse Density Enforcer .................................................................................................................. Local Loopback ............................................................................................................................. Power-up Sequence ....................................................................................................................... Remote Loopback.......................................................................................................................... 23 23 25 27 29 29
4.0 5.0
STATUS AND INFORMATION REGISTERS .......................................... 30 ERROR COUNT REGISTERS ................................................................ 38
Line Code Violation Count Register ............................................................................................. Path Code Violation Count Register.............................................................................................. Multiframes Out of SYNC Count Register ................................................................................... 39 39 40
6.0 7.0
DSO MONITORING FUNCTION ............................................................. 41 SIGNALING OPERATION....................................................................... 44
Processor Based Signaling.......................................................................................................... Hardware Based Signaling.......................................................................................................... 44 46
8.0
PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK.......... 47
Transmit Side Code Generation..................................................................................................... Receive Side Code Generation ...................................................................................................... 47 49
9.0
CLOCK BLOCKING REGISTERS .......................................................... 51
10.0 ELASTIC STORES OPERATION............................................................ 52 11.0 FDL/FS EXTRACTION AND INSERTION................................................ 53
HDLC and BOC Controller for the FDL....................................................................................... Legacy FDL Support ..................................................................................................................... D4/SLC-96 Operation.................................................................................................................... 53 63 64
12.0 PROGRAMMABLE IN-BAND CODE GENERATION AND DETECTION 65 13.0 TRANSMIT TRANSPARENCY................................................................ 68
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14.0 LINE INTERFACE FUNCTION................................................................ 69 15.0 TIMING DIAGRAMS................................................................................ 74
Transmit Data Flow Diagram ........................................................................................................ 80
16.0 CHARACTERISTICS .............................................................................. 81
Absolute Maximum Rating............................................................................................................ DC Parameters ............................................................................................................................... AC Parameters ............................................................................................................................... Timing............................................................................................................................................ Package Description ...................................................................................................................... 81 81 82 85 93
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1.0 INTRODUCTION
The DS2152 is a superset version of the popular DS2151 T1 Single-Chip Transceiver offering the new features listed below. All of the original features of the DS2151 have been retained and software created for the original devices is transferable into the DS2152.
New Features
option for non-multiplexed bus operation crystal-less jitter attenuation additional hardware signaling capability including: - receive signaling reinsertion to a backplane multiframe sync - availability of signaling in a separate PCM data stream - signaling freezing - interrupt generated on change of signaling data per-channel code insertion in both transmit and receive paths full HDLC controller for the FDL with 16-byte buffers in both transmit and receive paths RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state 8.192 MHz clock synthesizer per-channel loopback addition of hardware pins to indicate carrier loss & signaling freeze line interface function can be completely decoupled from the framer/formatter to allow: - interface to optical, HDSL, and other NRZ interfaces - ability to "tap" the transmit and receive bipolar data streams for monitoring purposes - ability to corrupt data and insert framing errors, CRC errors, etc. transmit and receive elastic stores now have independent backplane clocks ability to monitor one DS0 channel in both the transmit and receive paths access to the data streams in between the framer/formatter and the elastic stores AIS generation in the line interface that is independent of loopbacks ability to calculate and check CRC6 according to the Japanese standard ability to pass the F-bit position through the elastic stores in the 2.048 MHz backplane mode programmable in-band loop code generator and detector

Functional Description
The analog AMI/B8ZS waveform off the T1 line is transformer-coupled into the RRING and RTIP pins of the DS2152. The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing/multi-frame pattern. The DS2152 contains an active filter that reconstructs the analog received signal for the non-linear losses that occur in transmission. The device has a usable receive sensitivity of 0 dB to -36 dB, which allows the device to operate on cables up to 6000 feet in length. The receive side framer locates D4 (SLC-96) or ESF multiframe boundaries as well as detects incoming alarms, including carrier loss, loss of synchronization, blue (AIS) and yellow alarms. If needed, the receive side elastic store can be enabled in order to absorb the phase and frequency differences between the recovered T1 data stream and an asynchronous backplane clock which is provided at the RSYSCLK input. The clock applied at the RSYSCLK input can be either a 2.048 MHz clock or a 1.544 MHz clock. The RSYSCLK can be a bursty clock with speeds up to 8.192 MHz. The transmit side of the DS2152 is totally independent from the receive side in both the clock requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for T1 transmission. Once the data stream has been prepared for transmission, it is sent via the jitter attenuation mux to the waveshaping and line driver functions. The DS2152 will drive the T1 line from the 4 of 93
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TTIP and TRING pins via a coupling transformer. The line driver can handle both long (CSU) and short haul (DSX-1) lines.
Reader's Note
This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125 us frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by channel 1. Each channel is made up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used: D4 SLC-96 ESF B8ZS CRC Ft Fs FPS MF BOC HDLC FDL Superframe (12 frames per multiframe) Multiframe Structure Subscriber Loop Carrier - 96 Channels (SLC-96 is an AT&T registered trademark) Extended Superframe (24 frames per multiframe) Multiframe Structure Bipolar with 8 0 Subsitution Cyclical Redundancy Check Terminal Framing Pattern in D4 Signaling Framing Pattern in D4 Framing Pattern in ESF Multiframe Bit Oriented Code High Level Data Link Control Facility Data Link
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DS2152 ENHANCED T1 SINGLE-CHIP TRANSCEIVER Figure 1-1
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PIN LIST Table 1-1
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 SYMBOL RCHBLK NC 8MCLK NC NC RCL NC NC NC NC BTS LIUC 8XCLK TEST NC RTIP RRING RVDD RVSS RVSS MCLK XTALD NC RVSS
INT
NC NC NC TTIP TVSS TVDD TRING TCHBLK TLCLK TLINK NC TSYNC TPOSI TNEGI TCLKI TCLKO TNEGO TPOSO DVDD DVSS TCLK
TYPE O O O I I O I I I I O O O O O O I I/O I I I O O O I
DESCRIPTION Receive Channel Block No Connect 8.192 MHz Clock No Connect No Connect Receive Carrier Loss No Connect No Connect No Connect No Connect Bus Type Select Line Interface Connect Eight Times Clock Test No Connect Receive Analog Tip Input Receive Analog Ring Input Receive Analog Positive Supply Receive Analog Signal Ground Receive Analog Signal Ground Master Clock Input Quartz Crystal Driver No Connect Receive Analog Signal Ground Interrupt No Connect No Connect No Connect Transmit Analog Tip Output Transmit Analog Signal Ground Transmit Analog Positive Supply Transmit Analog Ring Output Transmit Channel Block Transmit Link Clock Transmit Link Data No Connect Transmit Sync Transmit Positive Data Input Transmit Negative Data Input Transmit Clock Input Transmit Clock Output Transmit Negative Data Output Transmit Positive Data Output Digital Positive Supply Digital Signal Ground Transmit Clock 7 of 93
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PIN 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93
SYMBOL TSER TSIG TESO TDATA TSYSCLK TSSYNC TCHCLK NC MUX D0/AD0 D1/AD1 D2/AD2 D3/AD3 DVSS DVDD D4/AD4 D5/AD5 D6/AD6 D7/AD7 A0 A1 A2 A3 A4 A5 A6 A7/ALE RD ( DS )
CS
NC WR (R/ W ) RLINK RKCLK DVSS DVDD RCLK DVDD DVSS RDATA RPOSI RNEGI RCLKI RCLKO RNEGO RPOSO RCHCLK RSIGF
TYPE I I O I I I O I I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I I O O O O I I I O O O O O
DESCRIPTION Transmit Serial Data Transmit Signaling Input Transmit Elastic Store Output Transmit Data Transmit System Clock Transmit System Sync Transmit Channel Clock No Connect Bus Operation Data Bus Bit 0 / Address/Data Bus Bit 0 Data Bus Bit 1 / Address/Data Bus Bit 1 Data Bus Bit 2 / Address/Data Bus Bit 2 Data Bus Bit 3 / Address/Data Bus Bit 3 Digital Signal Ground Digital Positive Supply Data Bus Bit 4 / Address/Data Bus Bit 4 Data Bus Bit 5 / Address/Data Bus Bit 5 Data Bus Bit 6 / Address/Data Bus Bit 6 Data Bus Bit 7 / Address/Data Bus Bit 7 Address Bus Bit 0 Address Bus Bit 1 Address Bus Bit 2 Address Bus Bit 3 Address Bus Bit 4 Address Bus Bit 5 Address Bus Bit 6 Address Bus Bit 7 / Address Latch Enable Read Input (Data Strobe) Chip Select No Connect Write Input (Read/Write) Receive Link Data Receive Link Clock Digital Signal Ground Digital Positive Supply Receive Clock Digital Positive Supply Digital Signal Ground Receive Data Receive Positive Data Input Receive Negative Data Input Receive Clock Input Receive Clock Output Receive Negative Data Output Receive Positive Data Output Receive Channel Clock Receive Signaling Freeze Output 8 of 93
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PIN 94 95 96 97 98 99 100
SYMBOL RSIG RSER RMSYNC RFSYNC RSYNC RLOS/LOTC RSYSCLK
TYPE O O O O I/O O I
DESCRIPTION Receive Signaling Output Receive Serial Data Receive Multiframe Sync Receive Frame Sync Receive Sync Receive Loss Of Sync / Loss of Transmit Clock Receive System Clock
NOTE:
Leave all no connect (NC) pins open circuited.
DS2152 PIN DESCRIPTION Table 1-2 TRANSMIT SIDE DIGITAL PINS
Transmit Clock [TCLK]. A 1.544 MHz primary clock. Used to clock data through the transmit side formatter. Transmit Serial Data [TSER]. Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. Transmit Channel Clock [TCHCLK]. A 192 kHz clock which pulses high during the LSB of each channel. Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for parallel to serial conversion of channel data. Transmit Channel Block [TCHBLK]. A user-programmable output that can be forced high or low during any of the 24 T1 channels. Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all T1 channels are used such as Fractional T1, 384 kbps (H0), 768 kbps or ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning. See Section 9 for details. Transmit System Clock [TSYSCLK]. 1.544 MHz or 2.048 MHz clock. Only used when the transmit side elastic store function is enabled. Should be tied low in applications that do not use the transmit side elastic store. Can be burst at rates up to 8.192 MHz. Transmit Link Clock [TLCLK]. 4 kHz or 2 kHz (ZBTSI) demand clock for the TLINK input. See Section 11 for details. Transmit Link Data [TLINK]. Transmit Link Data [TLINK]. If enabled via TCR1.2, this pin will be sampled on the falling edge of TCLK for data insertion into either the FDL stream (ESF) or the Fs-bit position (D4) or the Z-bit position (ZBTSI). See Section 11 for details. Transmit Sync [TSYNC]. A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Via TCR2.2, the DS2152 can be programmed to output either a frame or multiframe pulse 9 of 93
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at this pin. If this pin is set to output pulses at frame boundaries, it can also be set via TCR2.4 to output double-wide pulses at signaling frames. See Section 15 for details. Transmit System Sync [TSSYNC]. Only used when the transmit side elastic store is enabled. A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Should be tied low in applications that do not use the transmit side elastic store. Transmit Signaling Input [TSIG]. When enabled, this input will sample signaling bits for insertion into outgoing PCM T1 data stream. Sampled on the falling edge of TCLK when the transmit side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. Transmit Elastic Store Data Output [TESO]. Updated on the rising edge of TCLK with data out of the transmit side elastic store whether the elastic store is enabled or not. This pin is normally tied to TDATA. Transmit Data [TDATA]. Sampled on the falling edge of TCLK with data to be clocked through the transmit side formatter. This pin is normally tied to TESO. Transmit Positive Data Output [TPOSO]. Updated on the rising edge of TCLKO with the bipolar data out of the transmit side formatter. Can be programmed to source NRZ data via the Output Data Format (CCR1.6) control bit. This pin is normally tied to TPOSI. Transmit Negative Data Output [TNEGO]. Updated on the rising edge of TCLKO with the bipolar data out of the transmit side formatter. This pin is normally tied to TNEGI. Transmit Clock Output [TCLKO]. Buffered clock that is used to clock data through the transmit side formatter (i.e., either TCLK or RCLKI). This pin is normally tied to TCLKI. Transmit Positive Data Input [TPOSI]. Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TPOSO by tying the LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications. Transmit Negative Data Input [TNEGI]. Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TNEGO by tying the LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications. Transmit Clock Input [TCLKI]. Line interface transmit clock. Can be internally connected to TCLKO by tying the LIUC pin high.
RECEIVE SIDE DIGITAL PINS
Receive Link Data [RLINK]. Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a frame. See Section 15 for details. Receive Link Clock [RLCLK]. A 4 kHz or 2 kHz (ZBTSI) clock for the RLINK output. Receive Clock [RCLK]. 1.544 MHz clock that is used to clock data through the receive side framer. Receive Channel Clock [RCHCLK]. A 192 kHz clock which pulses high during the LSB of each channel. Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for parallel to serial conversion of channel data. 10 of 93
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Receive Channel Block [RCHBLK]. A user-programmable output that can be forced high or low during any of the 24 T1 channels. Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all T1 channels are used, such as Fractional T1, 384 kbps service, 768 kbps, or ISDN-PRI. Also useful for locating individual channels in drop-andinsert applications, for external per-channel loopback, and for per-channel conditioning. See Section 9 for details. Receive Serial Data [RSER]. Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled. Receive Sync [RSYNC]. An extracted pulse, one RCLK wide, is output at this pin which identifies either frame (RCR2.4=0) or multiframe (RCR2.4=1) boundaries. If set to output frame boundaries then via RCR2.5, RSYNC can also be set to output double-wide pulses on signaling frames. If the receive side elastic store is enabled via CCR1.2, then this pin can be enabled to be an input via RCR2.3 at which a frame or multiframe boundary pulse is applied. See Section 15 for details. Receive Frame Sync [RFSYNC]. An extracted 8 kHz pulse 1 RCLK wide is output at this pin which identifies frame boundaries. Receive Multiframe Sync [RMSYNC]. Only used when the receive side elastic store is enabled. An extracted pulse, 1 RSYSCLK wide, is output at this pin which identifies multiframe boundaries. If the receive side elastic store is disabled, then this output will output multiframe boundaries associated with RCLK. Receive Data [RDATA]. Updated on the rising edge of RCLK with the data out of the receive side framer. Receive System Clock [RSYSCLK]. 1.544 MHz or 2.048 MHz clock. Only used when the elastic store function is enabled. Should be tied low in applications that do not use the elastic store. Can be burst at rates up to 8.192 MHz. Receive Signaling Output [RSIG]. Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled. Receive Loss of Sync / Loss of Transmit Clock [RLOS/LOTC]. A dual function output that is controlled by the CCR3.5 control bit. This pin can be programmed to either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been toggled for 5 s. Receive Carrier Loss [RCL]. Set high when the line interface detects a loss of carrier. Receive Signaling Freeze [RSIGF]. Set high when the signaling data is frozen via either automatic or manual intervention. Used to alert downstream equipment of the condition. 8 MHz Clock [8MCLK]. A 8.192 MHz output clock that is referenced to the clock that is output at the RCLK pin and is used to clock data through the receive side framer.
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Receive Positive Data Output [RPOSO]. Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally tied to RPOSI. Receive Negative Data Output [RNEGO]. Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally tied to RNEGI. Receive Clock Output [RCLKO]. Buffered recovered clock from the T1 line. This pin is normally tied to RCLKI. Receive Positive Data Input [RPOSI]. Sampled on the falling edge of RCLKI for data to be clocked through the receive side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be internally connected to RPOSO by tying the LIUC pin high. Receive Negative Data Input [RNEGI]. Sampled on the falling edge of RCLKI for data to be clocked through the receive side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be internally connected to RNEGO by tying the LIUC pin high. Receive Clock Input [RCLKI]. Clock used to clock data through the receive side framer. This pin is normally tied to RCLKO. Can be internally connected to RCLKO by tying the LIUC pin high.
PARALLEL CONTROL PORT PINS
Interrupt [INT]. Flags host controller during conditions and change of conditions defined in the Status Registers 1 and 2 and the FDL Status Register. Active low, open drain output. 3-State Control [Test]. Set high to 3-state all output and I/O pins (including the parallel control port). Set low for normal operation. Useful in board-level testing. Bus Operation [MUX]. Set low to select non-multiplexed bus operation. Set high to select multiplexed bus operation. Data Bus [D0 to D7] or Address/Data Bus [AD0 to AD7]. In non-multiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation (MUX = 1), serves as an 8-bit multiplexed address/data bus. Address Bus [A0 to A6]. In non-multiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation (MUX = 1), these pins are not used and should be tied low. Bus Type Select [BTS]. Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the RD ( DS ), ALE(AS), and WR (R/ W ) pins. If BTS = 1, then these pins assume the function listed in parenthesis (). Read Input [ RD ] (Data Strobe [ DS ]). RD and DS are active low signals when MUX=1. DS is active high when MUX = 0. See bus timing diagrams. Chip Select [ CS ]. Must be low to read or write to the device. CS is an active low signal. A7 or Address Latch Enable [ALE] (Address Strobe [AS]). In non-multiplexed bus operation (MUX = 0), serves as the upper address bit. In multiplexed bus operation (MUX = 1), serves to demultiplex the bus on a positive-going edge. 12 of 93
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Write Input [ WR ] (Read/Write [R/ W ]). WR is an active low signal.
LINE INTERFACE PINS
Master Clock Input [MCLK]. A 1.544 MHz ( 50 ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data recovery and for jitter attenuation. A quartz crystal of 1.544 MHz may be applied across MCLK and XTALD instead of the TTL level clock source. Quartz Crystal Driver [XTALD]. A quartz crystal of 1.544 MHz may be applied across MCLK and XTALD instead of a TTL level clock source at MCLK. Leave open circuited if a TTL clock source is applied at MCLK. Eight Times Clock [8XCLK]. A 12.352 MHz clock that is frequency locked to the 1.544 MHz clock provided from the clock/data recovery block (if the jitter attenuator is enabled on the receive side) or from the TCLKI pin (if the jitter attenuator is enabled on the transmit side). Can be internally disabled via the TEST2 register if not needed. Line Interface Connect [LIUC]. Tie low to separate the line interface circuitry from the framer/formatter circuitry and activate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. Tie high to connect the line interface circuitry to the framer/formatter circuitry and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. When LIUC is tied high, the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins should be tied low. Receive Tip and Ring [RTIP & RRING]. Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the T1 line. See Section 14 for details. Transmit Tip and Ring [TTIP & TRING]. Analog line driver outputs. These pins connect via a 1:1.15 or 1:1.36 step-up transformer to the T1 line. See Section 14 for details. Receive Analog Positive Supply [RVDD]. 5.0 volts 5%. Should be tied to the DVDD and TVDD pins. Transmit Analog Positive Supply [TVDD]. 5.0 volts 5%. Should be tied to the RVDD and DVDD pins. Digital Signal Ground [DVSS]. Should be tied to the RVSS and TVSS pins. Receive Analog Signal Ground [RVSS]. 0.0 volts. Should be tied to the DVSS and TVSS pins. Transmit Analog Ground [TVSS]. 0.0 volts. Should be tied to the RVSS and DVSS pins.
SUPPLY PINS
Digital Positive Supply [DVDD]. 5.0 volts 5%. Should be tied to the RVDD and TVDD pins.
DS2152 REGISTER MAP Table 1-3
ADDRESS 00 01 02 03 04 R/W R/W R/W R/W R/W R/W REGISTER NAME FDL Control FDL Status FDL Interrupt Mask Receive Performance Report Message Receive Bit Oriented Code 13 of 93 REGISTER ABBREVIATION FDLC FDLS FIMR RPRM RBOC
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ADDRESS 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33
R/W R R/W R/W W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R/W R/W R/W R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
REGISTER NAME Receive FDL FIFO Transmit Performance Report Message Transmit Bit Oriented Code Transmit FDL FIFO Test 2 Common Control 7 not present not present not present not present Deceive ID Receive Information 3 Common Control 4 In-Band Code Control Transmit Code Definition Receive Up Code Definition Receive Down Code Definition Transmit Channel Control 1 Transmit Channel Control 2 Transmit Channel Control 3 Common Control 5 Transmit DS0 Monitor Receive Channel Control 1 Receive Channel Control 2 Receive Channel Control 3 Common Control 6 Receive DS0 Monitor Status 1 Status 2 Receive Information 1 Line Code Violation Count 1 Line Code Violation Count 2 Path Code Violation Count 1 Path Code Violation Count 2 Multiframe Out of Sync Count 2 Receive FDL Register Receive FDL Match 1 Receive FDL Match 2 Receive Control 1 Receive Control 2 Receive Mark 1 Receive Mark 2 Receive Mark 3 Common Control 3 Receive Information 2 Transmit Channel Blocking 1 Transmit Channel Blocking 2 14 of 93
REGISTER ABBREVIATION RFFR TPRM TBOC TFFR TEST2 (set to 00h) CCR7 IDR RIR3 CCR4 IBCC TCD RUPCD RDNCD TCC1 TCC2 TCC3 CCR5 TDS0M RCC1 RCC2 RCC3 CCR6 RDS0M SR1 SR2 RIR1 LCVCR1 LCVCR2 PCVCR1 PCVCR2 MOSCR2 RFDL RMTCH1 RMTCH2 RCR1 RCR2 RMR1 RMR2 RMR3 CCR3 RIR2 TCBR1 TCBR2
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ADDRESS 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R
REGISTER NAME Transmit Channel Blocking 3 Transmit Control 1 Transmit Control 2 Common Control 1 Common Control 2 Transmit Transparency 1 Transmit Transparency 2 Transmit Transparency 3 Transmit Idle 1 Transmit Idle 2 Transmit Idle 3 Transmit Idle Definition Transmit Channel 9 Transmit Channel 10 Transmit Channel 11 Transmit Channel 12 Transmit Channel 13 Transmit Channel 14 Transmit Channel 15 Transmit Channel 16 Transmit Channel 17 Transmit Channel 18 Transmit Channel 19 Transmit Channel 20 Transmit Channel 21 Transmit Channel 22 Transmit Channel 23 Transmit Channel 24 Transmit Channel 1 Transmit Channel 2 Transmit Channel 3 Transmit Channel 4 Transmit Channel 5 Transmit Channel 6 Transmit Channel 7 Transmit Channel 8 Receive Channel 1 Receive Channel 18 Receive Channel 19 Receive Channel 20 Receive Channel 21 Receive Channel 22 Receive Channel 23 Receive Channel 24 Receive Signaling 1 Receive Signaling 2 Receive Signaling 3 15 of 93
REGISTER ABBREVIATION TCBR3 TCR1 TCR2 CCR1 CCR2 TTR1 TTR2 TTR3 TIR1 TIR2 TIR3 TIDR TC9 TC10 TC11 TC12 TC13 TC14 TC15 TC16 TC17 TC18 TC19 TC20 TC21 TC22 TC23 TC24 TC1 TC2 TC3 TC4 TC5 TC6 TC7 TC8 RC17 RC18 RC19 RC20 RC21 RC22 RC23 RC24 RS1 RS2 RS3
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ADDRESS 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F
R/W R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
REGISTER NAME Receive Signaling 4 Receive Signaling 5 Receive Signaling 6 Receive Signaling 7 Receive Signaling 8 Receive Signaling 9 Receive Signaling 10 Receive Signaling 11 Receive Signaling 12 Receive Channel Blocking 1 Receive Channel Blocking 2 Receive Channel Blocking 3 Interrupt Mask 2 Transmit Signaling 1 Transmit Signaling 2 Transmit Signaling 3 Transmit Signaling 4 Transmit Signaling 5 Transmit Signaling 6 Transmit Signaling 7 Transmit Signaling 8 Transmit Signaling 9 Transmit Signaling 10 Transmit Signaling 11 Transmit Signaling 12 Line Interface Control Test 1 Transmit FDL Register Interrupt Mask Register 1 Receive Channel 1 Receive Channel 2 Receive Channel 3 Receive Channel 4 Receive Channel 5 Receive Channel 6 Receive Channel 7 Receive Channel 8 Receive Channel 9 Receive Channel 10 Receive Channel 11 Receive Channel 12 Receive Channel 13 Receive Channel 14 Receive Channel 15 Receive Channel 16
REGISTER ABBREVIATION RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RCBR1 RCBR2 RCBR3 IMR2 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 LICR TEST1 (set to 00h) TFDL IMR1 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 RC10 RC11 RC12 RC13 RC14 RC15 RC16
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NOTES:
1. Test Registers 1 and 2 are used only by the factory; these registers must be cleared (set to all 0s) on power-up initialization to insure proper operation. 2. Register banks 9xh, Axh, Bxh, Cxh, Dxh, Exh, and Fxh are not accessible.
2.0 PARALLEL PORT
The DS2152 is controlled via either a non-multiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. The DS2152 can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C. Electrical Characteristics in Section 16 for more details.
3.0 CONTROL, ID AND TEST REGISTERS
The operation of the DS2152 is configured via a set of eleven control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS2152 has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. There are two Receive Control Register (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2), and seven Common Control Registers (CCR1 to CCR7). Each of the eleven registers are described in this section. There is a device IDentification Register (IDR) at address 0Fh. The MSB of this read-only register is fixed to a 0 indicating that the DS2152 is present. The E1 pin-for-pin compatible version of the DS2152 is the DS2154, which also has an ID register at address 0Fh. The user can read the MSB to determine which chip is present since in the DS2152 the MSB will be set to a 0 and in the DS2154 it will be set to a 1. The lower 4 bits of the IDR are used to display the die revision of the chip.
IDR: DEVICE IDENTIFICATION REGISTER (Address=0F Hex)
(MSB) T1E1 0 0 POSITION IDR.7 0 ID3 ID2 ID1 (LSB) ID0
SYMBOL T1E1
NAME AND DESCRIPTION T1 or E1 Chip Determination Bit. 0=T1 chip 1=E1 chip Chip Revision Bit 3. MSB of a decimal code that represents the chip revision. Chip Revision Bit 2. Chip Revision Bit 1. Chip Revision Bit 0. LSB of a decimal code that represents the chip revision.
ID3
IDR.3
ID2 ID1 ID0
IDR.1 IDR.2 IDR.0
The two Test Registers at addresses 09 and 7D hex are used by the factory in testing the DS2152. On power-up, the Test Registers should be set to 00 hex in order for the DS2152 to operate properly. 17 of 93
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RCR1: RECEIVE CONTROL REGISTER 1 (Address=2B Hex)
(MSB) LCVCRF ARC OOF1 POSITION RCR1.7 OOF2 SYNCC SYNCT SYNCE (LSB) RESYNC
SYMBOL LCVCRF
NAME AND DESCRIPTION Line Code Violation Count Register Function Select. 0 = do not count excessive 0s 1 = count excessive 0s Auto Resync Criteria. 0 = Resync on OOF or RCL event 1 = Resync on OOF only Out Of Frame Select 1. 0 = 2/4 frame bits in error 1 = 2/5 frame bits in error Out Of Frame Select 2. 0 = follow RCR1.5 1 = 2/6 frame bits in error Sync Criteria. In D4 Framing Mode 0 = search for Ft pattern, then search for Fs pattern 1 = cross couple Ft and Fs pattern In ESF Framing Mode 0 = search for FPS pattern only 1 = search for FPS and verify with CRC6 Sync Time. 0 = qualify 10 bits 1 = qualify 24 bits Sync Enable. 0 = auto resync enabled 1 = auto resync disabled Resync. When toggled from low to high, a resynchronization of the receive side framer is initiated. Must be cleared and set again for a subsequent resync.
ARC
RCR1.6
OOF1
RCR1.5
OOF2
RCR1.4
SYNCC
RCR1.3
SYNCT
RCR1.2
SYNCE
RCR1.1
RESYNC
RCR1.0
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RCR2: RECEIVE CONTROL REGISTER 2 (Address=2C Hex)
(MSB) RCS RZBTSI RSDW RSM RSIO RD4YM FSBE (LSB) MOSCRF
SYMBOL RCS
POSITION RCR2.7
NAME AND DESCRIPTION Receive Code Select. See Section 8 for more details. 0 = idle code (7F Hex) 1 = digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex) Receive Side ZBTSI Enable. 0 = ZBTSI disabled 1 = ZBTSI enabled RSYNC Double-Wide. (note: this bit must be set to 0 when RCR2.4 = 1 or when RCR2.3 = 1) 0 = do not pulse double-wide in signaling frames 1 = do pulse double-wide in signaling frames RSYNC Mode Select. (A Don't Care if RSYNC is programmed as an input) 0 = frame mode (see the timing in Section 15) 1 = multiframe mode (see the timing in Section 15) RSYNC I/O Select. (note: this bit must be set to 0 when CCR1.2 = 0) 0 = RSYNC is an output 1 = RSYNC is an input (only valid if elastic store enabled) Receive Side D4 Yellow Alarm Select. 0 = 0s in bit 2 of all channels 1 = a 1 in the S-bit position of frame 12 PCVCR Fs-Bit Error Report Enable. 0 = do not report bit errors in Fs-bit position; only Ft bit position 1 = report bit errors in Fs-bit position as well as Ft bit position Multiframe Out of Sync Count Register Function Select. 0 = count errors in the framing bit position 1 = count the number of multiframes out of sync
RZBTSI
RCR2.6
RSDW
RCR2.5
RSM
RCR2.4
RSIO
RCR2.3
RD4YM
RCR2.2
FSBE
RCR2.1
MOSCRF
RCR2.0
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TCR1: TRANSMIT CONTROL REGISTER 1 (Address=35 Hex)
(MSB) LOTCMC TFPT TCPT POSITION TCR1.7 TSSE GB7S TFDLS TBL (LSB) TYEL
SYMBOL LOTCMC
NAME AND DESCRIPTION Loss Of Transmit Clock Mux Control. Determines whether the transmit side formatter should switch to the ever present RCLKO if the TCLK input should fail to transition (see Figure 1-1 for details). 0 = do not switch to RCLKO if TCLK stops 1 = switch to RCLKO if TCLK stops Transmit F-Bit Pass Through. (see note below) 0 = F bits sourced internally 1 = F bits sampled at TSER Transmit CRC Pass Through. (see note below) 0 = source CRC6 bits internally 1 = CRC6 bits sampled at TSER during F-bit time Software Signaling Insertion Enable. (see note below) 0 = no signaling is inserted in any channel - from the TS1-TS12 registers 1 = signaling is inserted in all channels - from the TS1-TS12 registers (the TTR registers can be used to block insertion on a channel by channel basis) Global Bit 7 Stuffing. (see note below) 0 = allow the TTR registers to determine which channels containing all 0s are to be Bit 7 stuffed 1 = force Bit 7 stuffing in all 0-byte channels regardless of how the TTR registers are programmed TFDL Register Select. (see note below) 0 = source FDL or Fs bits from the internal TFDL register (legacy FDL support mode) 1 = source FDL or Fs bits from the internal HDLC/BOC controller or the TLINK pin Transmit Blue Alarm. (see note below) 0 = transmit data normally 1 = transmit an unframed all 1s code at TPOSO and TNEGO Transmit Yellow Alarm. (see note below) 0 = do not transmit yellow alarm 1 = transmit yellow alarm
TFPT
TCR1.6
TCPT
TCR1.5
TSSE
TCR1.4
GB7S
TCR1.3
TFDLS
TCR1.2
TBL
TCR1.1
TYEL
TCR1.0
NOTE:
For a description of how the bits in TCR1 affect the transmit side formatter, see Figure 15-11.
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TCR2: TRANSMIT CONTROL REGISTER 2 (Address=36 Hex)
(MSB) TEST1 TEST0 TZBTSI POSITION TCR2.7 TCR2.6 TCR2.5 TSDW TSM TSIO TD4YM (LSB) TB7ZS
SYMBOL TEST1 TEST0 TZBTSI
NAME AND DESCRIPTION Test Mode Bit 1 for Output Pins. See Table 3-1. Test Mode Bit 0 for Output Pins. See Table 3-1. Transmit Side ZBTSI Enable. 0 = ZBTSI disabled 1 = ZBTSI enabled TSYNC Double-Wide. (note: this bit must be set to 0 when TCR2.3=1 or when TCR2.2=0) 0 = do not pulse double-wide in signaling frames 1 = do pulse double-wide in signaling frames TSYNC Mode Select. 0 = frame mode (see the timing in Section 15) 1 = multiframe mode (see the timing in Section 15) TSYNC I/O Select. 0 = TSYNC is an input 1 = TSYNC is an output Transmit Side D4 Yellow Alarm Select. 0 = 0s in bit 2 of all channels 1 = a 1 in the S-bit position of frame 12 Transmit Side Bit 7 0 Suppression Enable. 0 = no stuffing occurs 1 = Bit 7 force to a 1 in channels with all 0s
TSDW
TCR2.4
TSM
TCR2.3
TSIO
TCR2.2
TD4YM
TCR2.1
TB7ZS
TCR2.0
OUTPUT PIN TEST MODES Table 3-1
TEST 1 0 0 1 1 TEST 0 0 1 0 1 EFFECT ON OUTPUT PINS operate normally force all output pins 3-state (including all I/O pins and parallel port pins) force all output pins low (including all I/O pins except parallel port pins) force all output pins high (including all I/O pins except parallel port pins)
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CCR1: COMMON CONTROL REGISTER 1 (Address=37 Hex)
(MSB) TESE ODF RSAO POSITION CCR1.7 TSCLKM RSCLKM RESE PLB (LSB) FLB
SYMBOL TESE
NAME AND DESCRIPTION Transmit Elastic Store Enable. 0 = elastic store is bypassed 1 = elastic store is enabled Output Data Format. 0 = bipolar data at TPOSO and TNEGO 1 = NRZ data at TPOSO; TNEGO = 0 Receive Signaling All 1s. This bit should not be enabled if hardware signaling is being utilized. See Section 7 for more details. 0 = allow robbed signaling bits to appear at RSER 1 = force all robbed signaling bits at RSER to 1 TSYSCLK Mode Select. 0 = if TSYSCLK is 1.544 MHz 1 = if TSYSCLK is 2.048 MHz RSYSCLK Mode Select. 0 = if RSYSCLK is 1.544 MHz 1 = if RSYSCLK is 2.048 MHz Receive Elastic Store Enable. 0 = elastic store is bypassed 1 = elastic store is enabled Payload Loopback. 0 = loopback disabled 1 = loopback enabled Framer Loopback. 0 = loopback disabled 1 = loopback enabled
ODF
CCR1.6
RSAO
CCR1.5
TSCLKM
CCR1.4
RSCLKM
CCR1.3
RESE
CCR1.2
PLB
CCR1.1
FLB
CCR1.0
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Payload Loopback
When CCR1.1 is set to a 1, the DS2152 will be forced into Payload LoopBack (PLB). Normally, this loopback is only enabled when ESF framing is being performed but can be enabled also in D4 framing applications. In a PLB situation, the DS2152 will loop the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are reinserted by the DS2152. When PLB is enabled, the following will occur: 1. data will be transmitted from the TPOSO and TNEGO pins synchronous with RCLK instead of TCLK 2. all of the receive side signals will continue to operate normally 3. the TCHCLK and TCHBLK signals are forced low 4. data at the TSER, TDATA, and TSIG pins is ignored 5. the TLCLK signal will become synchronous with RCLK instead of TCLK.
Framer Loopback
When CCR1.0 is set to a 1, the DS2152 will enter a Framer LoopBack (FLB) mode. This loopback is useful in testing and debugging applications. In FLB, the DS2152 will loop data from the transmit side back to the receive side. When FLB is enabled, the following will occur: 1. an unframed all 1s code will be transmitted at TPOSO and TNEGO 2. data at RPOSI and RNEGI will be ignored 3. all receive side signals will take on timing synchronous with TCLK instead of RCLKI. Please note that it is not acceptable to have RCLK tied to TCLK during this loopback because this will cause an unstable condition.
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CCR2: COMMON CONTROL REGISTER 2 (Address=38 Hex)
(MSB) TFM TB8ZS TSLC96 POSITION CCR2.7 TFDL RFM RB8ZS RSLC96 (LSB) RFDL
SYMBOL TFM
NAME AND DESCRIPTION Transmit Frame Mode Select. 0 = D4 framing mode 1 = ESF framing mode Transmit B8ZS Enable. 0 = B8ZS disabled 1 = B8ZS enabled Transmit SLC-96 / Fs-Bit Loading Enable. Only set this bit to a 1 in D4 framing applications. Must be set to 1 to source the Fs pattern. See Section 11 for details. 0 = SLC-96/Fs-bit loading disabled 1 = SLC-96/Fs-bit loading enabled Transmit FDL 0 Stuffer Enable. Set this bit to 0 if using the internal HDLC/BOC controller instead of the legacy support for the FDL. See Section 11 for details. 0 = 0 stuffer disabled 1 = 0 stuffer enabled Receive Frame Mode Select. 0 = D4 framing mode 1 = ESF framing mode Receive B8ZS Enable. 0 = B8ZS disabled 1 = B8ZS enabled Receive SLC-96 Enable. Only set this bit to a 1 in D4/SLC-96 framing applications. See Section 11 for details. 0 = SLC-96 disabled 1 = SLC-96 enabled Receive FDL 0 Destuffer Enable. Set this bit to 0 if using the internal HDLC/BOC controller instead of the legacy support for the FDL. See Section 11 for details. 0 = 0 destuffer disabled 1 = 0 destuffer enabled
TB8ZS
CCR2.6
TSLC96
CCR2.5
TFDL
CCR2.4
RFM
CCR2.3
RB8ZS
CCR2.2
RSLC96
CCR2.1
RFDL
CCR2.0
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CCR3: COMMON CONTROL REGISTER 3 (Address=30 Hex)
(MSB) ESMDM ESR RLOSF POSITION CCR3.7 RSMS PDE ECUS TLOOP (LSB) -
SYMBOL ESMDM
NAME AND DESCRIPTION Elastic Store Minimum Delay Mode. See Section 10.3 for details. 0 = elastic stores operate at full two-frame depth 1 = elastic stores operate at 32-bit depth Elastic Store Reset. Setting this bit from a 0 to a 1 will force the elastic stores to a known depth. Should be toggled after RSYSCLK and TSYSCLK have been applied and are stable. Must be cleared and set again for a subsequent reset. Function of the RLOS/LOTC Output. 0 = Receive Loss of Sync (RLOS) 1 = Loss of Transmit Clock (LOTC) RSYNC Multiframe Skip Control. Useful in framing format conversions from D4 to ESF. This function is not available when the receive side elastic store is enabled. 0 = RSYNC will output a pulse at every multiframe 1 = RSYNC will output a pulse at every other multiframe note: for this bit to have any affect, the RSYNC must be set to output multiframe pulses (RCR2.4=1 and RCR2.3=0). Pulse Density Enforcer Enable. 0 = disable transmit pulse density enforcer 1 = enable transmit pulse density enforcer Error Counter Update Select. See Section 5 for details. 0 = update error counters once a second 1 = update error counters every 42 ms (333 frames) Transmit Loop Code Enable. See Section 12 for details. 0 = transmit data normally 1 = replace normal transmitted data with repeating code as defined in TCD register Not Assigned. Must be set to 0 when written.
ESR
CCR3.6
RLOSF
CCR3.5
RSMS
CCR3.4
PDE
CCR3.3
ECUS
CCR3.2
TLOOP
CCR3.1
-
CCR3.0
Pulse Density Enforcer
The SCT always examines both the transmit and receive data streams for violations of the following rules which are required by ANSI T1.403: no more than 15 consecutive 0s at least N 1s in each and every time window of 8 x (N +1) bits where N = 1 through 23
Violations for the transmit and receive data streams are reported in the RIR2.0 and RIR2.1 bits respectively. When the CCR3.3 is set to 1, the DS2152 will force the transmitted stream to meet this requirement no matter the content of the transmitted stream. When running B8ZS, the CCR3.3 bit should be set to 0 since B8ZS encoded data streams cannot violate the pulse density requirements. 25 of 93
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CCR4: COMMON CONTROL REGISTER 4 (Address=11 Hex)
(MSB) RSRE RSRE RPCSI RFSA1 RFE RFF THSE TPCSI (LSB) TIRFS
SYMBOL
POSITION CCR4.7
NAME AND DESCRIPTION Receive Side Signaling Reinsertion Enable. See Section 7.2 for details. 0 = do not re-insert signaling bits into the data stream presented at the RSER pin 1 = re-insert the signaling bits into data stream presented at the RSER pin Receive Per-Channel Signaling Insert. See Section 7.2 for more details. 0 = do not use RCHBLK to determine which channels should have signaling re-inserted 1 = use RCHBLK to determine which channels should have signaling re-inserted Receive Force Signaling All 1s. See Section 7.2 for more details. 0 = do not force extracted robbed-bit signaling bit positions to a 1 1 = force extracted robbed-bit signaling bit positions to a 1 Receive Freeze Enable. See Section 7.2 for details. 0 = no freezing of receive signaling data will occur 1 = allow freezing of receive signaling data at RSIG (and RSER if CCR4.7 = 1). Receive Force Freeze. Freezes receive side signaling at RSIG (and RSER if CCR4.7=1); will override Receive Freeze Enable (RFE). See Section 7.2 for details. 0 = do not force a freeze event 1 = force a freeze event Transmit Hardware Signaling Insertion Enable. See Section 7.2 for details. 0 = do not insert signaling from the TSIG pin into the data stream presented at the TSER pin 1 = insert the signaling from the TSIG pin into data stream presented at the TSER pin Transmit Per-Channel Signaling Insert. See Section 7.2 for details. 0 = do not use TCHBLK to determine which channels should have signaling inserted from TSIG 1 = use TCHBLK to determine which channels should have signaling inserted from TSIG Transmit Idle Registers (TIR) Function Select. See Section 8 for timing details. 0 = TIRs define in which channels to insert idle code 1 = TIRs define in which channels to insert data from RSER (i.e., Per-Channel Loopback function)
RPCSI
CCR4.6
RFSA1
CCR4.5
RFE
CCR4.4
RFF
CCR4.3
THSE
CCR4.2
TPCSI
CCR4.1
TIRFS
CCR4.0
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CCR5: COMMON CONTROL REGISTER 5 (Address=19 Hex)
(MSB) TJC LLB LIAIS POSITION CCR5.7 TCM4 TCM3 TCM2 TCM1 (LSB) TCM0
SYMBOL TJC
NAME AND DESCRIPTION Transmit Japanese CRC6 Enable. 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT-G704 CRC6 calculation Local Loopback. 0 = loopback disabled 1 = loopback enabled Line Interface AIS Generation Enable. See Figure 1-1 for details. 0 = allow normal data from TPOSI/TNEGI to be transmitted at TTIP and TRING 1 = force unframed all 1s to be transmitted at TTIP and TRING Transmit Channel Monitor Bit 4. MSB of a channel decode that determines which transmit channel data will appear in the TDS0M register. See Section 6 for details. Transmit Channel Monitor Bit 3. Transmit Channel Monitor Bit 2. Transmit Channel Monitor Bit 1. Transmit Channel Monitor Bit 0. LSB of the channel decode.
LLB
CCR5.6
LIAIS
CCR5.5
TCM4
CCR5.4
TCM3 TCM2 TCM1 TCM0
CCR5.3 CCR5.2 CCR5.1 CCR5.0
Local Loopback
When CCR5.6 is set to a 1, the DS2152 will be forced into Local LoopBack (LLB). In this loopback, data will continue to be transmitted as normal through the transmit side of the DS2152 (unless LIAIS = 1). Data being received at RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass through the jitter attenuator. Please see Figure 1-1 for more details. Please note that it is not acceptable to have RCLKO tied to TCLKI during this loopback because this will cause an unstable condition. Also it is recommended that the jitter attenuator be placed on the transmit side during this loopback.
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CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex)
(MSB) RJC POSITION CCR6.7 RCM4 RCM3 RCM2 RCM1 (LSB) RCM0
SYMBOL RJC
NAME AND DESCRIPTION Receive Japanese CRC6 Enable. 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT-G704 CRC6 calculation Not Assigned. Should be set to 0 when written. Not Assigned. Should be set to 0 when written. Receive Channel Monitor Bit 4. MSB of a channel decode that determines which receive channel data will appear in the RDS0M register. See Section 6 for details. Receive Channel Monitor Bit 3. Receive Channel Monitor Bit 2. Receive Channel Monitor Bit 1. Receive Channel Monitor Bit 0. LSB of the channel decode.
RCM4
CCR6.6 CCR6.5 CCR6.4
RCM3 RCM2 RCM1 RCM0
CCR6.3 CCR6.2 CCR6.1 CCR6.0
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CCR7: COMMON CONTROL REGISTER 7 (Address=0A Hex)
(MSB) LIRST RLB POSITION CCR7.7 (LSB) -
SYMBOL LIRST
NAME AND DESCRIPTION Line Interface reset. Setting this bit from a 0 to a 1 will initiate an internal reset that affects the clock recovery state machine and jitter attenuator. Normally this bit is only toggled on power-up. Must be cleared and set again for a subsequent reset. Remote Loopback. 0 = loopback disabled 1 = loopback enabled Not Assigned. Should be set to 0 when written to. Not Assigned. Should be set to 0 when written to. Not Assigned. Should be set to 0 when written to. Not Assigned. Should be set to 0 when written to. Not Assigned. Should be set to 0 when written to. Not Assigned. Should be set to 0 when written to.
RLB
CCR7.6
-
CCR7.5 CCR7.4 CCR7.3 CCR7.2 CCR7.1 CCR7.0
Power-Up Sequence
On power-up, after the supplies are stable, the DS2152 should be configured for operation by writing to all of the internal registers (this includes setting the Test Registers to 00Hex) since the contents of the internal registers cannot be predicted on power-up. Finally, after the TSYSCLK and RSYSCLK inputs are stable, the ESR bit should be toggled from a 0 to a 1 (this step can be skipped if the elastic stores are disabled).
Remote Loopback
When CCR7.6 is set to a 1, the DS2152 will be forced into Remote LoopBack (RLB). In this loopback, data input via the RPOSI and RNEGI pins will be transmitted back to the TPOSO and TNEGO pins. Data will continue to pass through the receive side framer of the DS2152 as it would normally and the data from the transmit side formatter will be ignored. Please see Figure 1-1 for more details.
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4.0 STATUS AND INFORMATION REGISTERS
There is a set of nine registers that contain information on the current real time status of the DS2152, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Registers 1 to 3 (RIR1/RIR2/RIR3) and a set of four registers for the onboard HDLC and BOC controller for the FDL. The specific details on the four registers pertaining to the FDL are covered in Section 11.1, but they operate the same as the other status registers in the DS2152 and this operation is described below. When a particular event has occurred (or is occurring), the appropriate bit in one of these nine registers will be set to a 1. All of the bits in SR1, SR2, RIR1, RIR2, and RIR3 registers operate in a latched fashion. This means that if an event or an alarm occurs and a bit is set to a 1 in any of the registers, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again (or in the case of the RBL, RYEL, LRCL, and RLOS alarms, the bit will remain set if the alarm is still present). There are bits in the four FDL status registers that are not latched and these bits are listed in Section 11.1. The user will always proceed a read of any of the nine registers with a write. The byte written to the register will inform the DS2152 which bits the user wishes to read and have cleared. The user will write a byte to one of these registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit location, the read register will be updated with the latest information. When a 0 is written to a bit position, the read register will not be updated and the previous value will be held. A write to the status and information registers will be immediately followed by a read of the same register. The read result should be logically AND'ed with the mask byte that was just written, and this value should be written back into the same register to insure that bit does indeed clear. This second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. This write-read-write scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS2152 with higher-order software languages. The SR1, SR2, and FDLS registers have the unique ability to initiate a hardware interrupt via the INT output pin. Each of the alarms and events in the SR1, SR2, and FDLS can be either masked or unmasked from the interrupt pin via the Interrupt Mask Register 1 (IMR1), Interrupt Mask Register 2 (IMR2), and FDL Interrupt Mask Register (FIMR) respectively. The FIMR register is covered in Section 11.1. The interrupts caused by alarms in SR1 (namely RYEL, LRCL, RBL, and RLOS) act differently than the interrupts caused by events in SR1 and SR2 (namely LUP, LDN, LOTC, RSLIP, RMF, TMF, SEC, RFDL, TFDL, RMTCH, RAF, and RSC) and FIMR. The alarm caused interrupts will force the INT pin low whenever the alarm changes state (i.e., the alarm goes active or inactive according to the set/clear criteria in Table 4-2). The INT pin will be allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the interrupt to occur even if the alarm is still present. The event caused interrupts will force the INT pin low when the event occurs. The INT pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.
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DS2152
RIR1: RECEIVE INFORMATION REGISTER 1 (Address=22 Hex)
(MSB) COFA 8ZD 16ZD POSITION RIR1.7 RESF RESE SEFE B8ZS (LSB) FBE
SYMBOL COFA
NAME AND DESCRIPTION Change of Frame Alignment. Set when the last resync resulted in a change of frame or multiframe alignment. Eight-0 Detect. Set when a string of at least eight consecutive 0s (regardless of the length of the string) have been received at RPOSI and RNEGI. Sixteen-0 Detect. Set when a string of at least 16 consecutive 0s (regardless of the length of the string) have been received at RPOSI and RNEGI. Receive Elastic Store Full. Set when the receive elastic store buffer fills and a frame is deleted. Receive Elastic Store Empty. Set when the receive elastic store buffer empties and a frame is repeated. Severely Errored Framing Event. Set when 2 out of 6 framing bits (Ft or FPS) are received in error. B8ZS Code Word Detect. Set when a B8ZS code word is detected at RPOS and RNEG independent of whether the B8ZS mode is selected or not via CCR2.6. Useful for automatically setting the line coding. Frame Bit Error. Set when a Ft (D4) or FPS (ESF) framing bit is received in error.
8ZD
RIR1.6
16ZD
RIR1.5
RESF
RIR1.4
RESE
RIR1.3
SEFE
RIR1.2
B8ZS
RIR1.1
FBE
RIR1.0
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RIR2: RECEIVE INFORMATION REGISTER 2 (Address=31 Hex)
(MSB) RLOSC LRCLC TESF TESE TSLIP RBLC RPDV (LSB) TPDV
SYMBOL RLOSC
POSITION RIR2.7
NAME AND DESCRIPTION Receive Loss of Sync Clear. Set when the framer achieves synchronization; will remain set until read. Line Interface Receive Carrier Loss Clear. Set when the carrier signal is restored; will remain set until read. See Table 4-2. Transmit Elastic Store Full. Set when the transmit elastic store buffer fills and a frame is deleted. Transmit Elastic Store Empty. Set when the transmit elastic store buffer empties and a frame is repeated. Transmit Elastic Store Slip Occurrence. Set when the transmit elastic store has either repeated or deleted a frame. Receive Blue Alarm Clear. Set when the Blue Alarm (AIS) is no longer detected; will remain set until read. See Table 4-2. Receive Pulse Density Violation. Set when the receive data stream does not meet the ANSI T1.403 requirements for pulse density. Transmit Pulse Density Violation. Set when the transmit data stream does not meet the ANSI T1.403 requirements for pulse density.
LRCLC
RIR2.6
TESF
RIR2.5
TESE
RIR2.4
TSLIP
RIR2.3
RBLC
RIR2.2
RPDV
RIR2.1
TPDV
RIR2.0
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RIR3: RECEIVE INFORMATION REGISTER 3 (Address=10 Hex)
(MSB) RL1 RL0 JALT POSITION RIR3.7 RIR3.6 RIR3.5 LORC FRCL (LSB) -
SYMBOL RL1 RL0 JALT
NAME AND DESCRIPTION Receive Level Bit 1. See Table 4-1. Receive Level Bit 0. See Table 4-1. Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches to within 4 bits of its limit; useful for debugging jitter attenuation operation. Loss of Receive Clock. Set when the RCLKI pin has not transitioned for at least 2 us (3 us 1 us). Framer Receive Carrier Loss. Set when 192 consecutive 0s have been received at the RPOSI and RNEGI pins; allowed to be cleared when 14 or more 1s out of 112 possible bit positions are received. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read.
LORC
RIR3.4
FRCL
RIR3.3
-
RIR3.2 RIR3.1 RIR3.0
DS2152 RECEIVE T1 LEVEL INDICATION Table 4-1
RL1 0 0 1 1 RL0 0 1 0 1 TYPICAL LEVEL RECEIVED +2 dB to -7.5 db -7.5 dB to -15 db -15 dB to -22.5 db less than -22.5 db
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SR1: STATUS REGISTER 1 (Address=20 Hex)
(MSB) LUP LDN LOTC POSITION SR1.7 RSLIP RBL RYEL LRCL (LSB) RLOS
SYMBOL LUP
NAME AND DESCRIPTION Loop Up Code Detected. Set when the loop up code as defined in the RUPCD register is being received. See Section 12 for details. Loop Down Code Detected. Set when the loop down code as defined in the RDNCD register is being received. See Section 12 for details. Loss of Transmit Clock. Set when the TCLK pin has not transitioned for one channel time (or 5.2 us). Will force the RLOS/LOTC pin high if enabled via CCR1.6. Also will force transmit side formatter to switch to RCLKO if so enabled via TCR1.7. Receive Elastic Store Slip Occurrence. Set when the receive elastic store has either repeated or deleted a frame. Receive Blue Alarm. Set when an unframed all 1s code is received at RPOSI and RNEGI. Receive Yellow Alarm. Set when a yellow alarm is received at RPOSI and RNEGI. Line Interface Receive Carrier Loss. Set when 192 consecutive 0s have been detected at RTIP and RRING. See Table 4-2. Receive Loss of Sync. Set when the device is not synchronized to the receive T1 stream.
LDN
SR1.6
LOTC
SR1.5
RSLIP
SR1.4
RBL
SR1.3
RYEL
SR1.2
LRCL
SR1.1
RLOS
SR1.0
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ALARM CRITERIA Table 4-2
ALARM Blue Alarm (AIS) (see note 1 below) Yellow Alarm (RAI) 1. D4 bit 2 mode(RCR2.2=0) 2. D4 12th F-bit mode (RCR2.2=1; this mode is also referred to as the "Japanese Yellow Alarm" 3. ESF mode Red Alarm (LRCL) (this alarm is also referred to as Loss Of Signal) SET CRITERIA when over a 3ms window, five or less 0s are received when bit 2 of 256 consecutive channels is set to 0 for at least 254 occurrences when the 12th framing bit is set to 1 for two consecutive occurrences CLEAR CRITERIA when over a 3 ms window, six or more 0s are received when bit 2 of 256 consecutive channels is set to 0 for less than 254 occurrences when the 12th framing bit is set to 0 for two consecutive occurrences
when 16 consecutive patterns of 00FF appear in the FDL when 192 consecutive 0s are received
when 14 or less patterns of 00FF hex out of 16 possible appear in the FDL when 14 or more 1s out of 112 possible bit positions are received starting with the first one received
NOTES:
1. The definition of Blue Alarm (or Alarm Indication Signal) is an unframed all 1s signal. Blue alarm detectors should be able to operate properly in the presence of a 10-3 error rate and they should not falsely trigger on a framed all 1s signal. The blue alarm criteria in the DS2152 have been set to achieve this performance. It is recommended that the RBL bit be qualified with the RLOS bit. 2. ANSI specifications use a different nomenclature than the DS2152 does; the following terms are equivalent: RBL = AIS LRCL = LOS RLOS = LOF RYEL = RAI
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SR2: STATUS REGISTER 2 (Address=21 Hex)
(MSB) RMF TMF SEC POSITION SR2.7 SR2.6 SR2.5 RFDL TFDL RMTCH RAF (LSB) RSC
SYMBOL RMF TMF SEC
NAME AND DESCRIPTION Receive Multiframe. Set on receive multiframe boundaries. Transmit Multiframe. Set on transmit multiframe boundaries. 1-Second Timer. Set on increments of 1 second based on RCLK; will be set in increments of 999 ms, 999 ms, and 1002 ms every 3 seconds. Receive FDL Buffer Full. Set when the receive FDL buffer (RFDL) fills to capacity (8 bits). Transmit FDL Buffer Empty. Set when the transmit FDL buffer (TFDL) empties. Receive FDL Match Occurrence. Set when the RFDL matches either RFDLM1 or RFDLM2. Receive FDL Abort. Set when eight consecutive 1s are received in the FDL. Receive Signaling Change. Set when the DS2152 detects a change of state in any of the robbed-bit signaling bits.
RFDL
SR2.4
TFDL
SR2.3
RMTCH
SR2.2
RAF
SR2.1
RSC
SR2.0
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IMR1: INTERRUPT MASK REGISTER 1 (Address=7F Hex)
(MSB) LUP LDN LOTC POSITION IMR1.7 SLIP RBL RYEL LRCL (LSB) RLOS
SYMBOL LUP
NAME AND DESCRIPTION Loop Up Code Detected. 0 = interrupt masked 1 = interrupt enabled Loop Down Code Detected. 0 = interrupt masked 1 = interrupt enabled Loss of Transmit Clock. 0 = interrupt masked 1 = interrupt enabled Elastic Store Slip Occurrence. 0 = interrupt masked 1 = interrupt enabled Receive Blue Alarm. 0 = interrupt masked 1 = interrupt enabled Receive Yellow Alarm. 0 = interrupt masked 1 = interrupt enabled Line Interface Receive Carrier Loss. 0 = interrupt masked 1 = interrupt enabled Receive Loss of Sync. 0 = interrupt masked 1 = interrupt enabled
LDN
IMR1.6
LOTC
IMR1.5
SLIP
IMR1.4
RBL
IMR1.3
RYEL
IMR1.2
LRCL
IMR1.1
RLOS
IMR1.0
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IMR2: INTERRUPT MASK REGISTER 2 (Address=6F Hex)
(MSB) RMF TMF SEC POSITION IMR2.7 RFDL TFDL RMTCH RAF (LSB) RSC
SYMBOL RMF
NAME AND DESCRIPTION Receive Multiframe. 0 = interrupt masked 1 = interrupt enabled Transmit Multiframe. 0 = interrupt masked 1 = interrupt enabled 1-Second Timer. 0 = interrupt masked 1 = interrupt enabled Receive FDL Buffer Full. 0 = interrupt masked 1 = interrupt enabled Transmit FDL Buffer Empty. 0 = interrupt masked 1 = interrupt enabled Receive FDL Match Occurrence. 0 = interrupt masked 1 = interrupt enabled Receive FDL Abort. 0 = interrupt masked 1 = interrupt enabled Receive Signaling Change. 0 = interrupt masked 1 = interrupt enabled
TMF
IMR2.6
SEC
IMR2.5
RFDL
IMR2.4
TFDL
IMR2.3
RMTCH
IMR2.2
RAF
IMR2.1
RSC
IMR2.0
5.0 ERROR COUNT REGISTERS
There are a set of three counters in the DS2152 that record bipolar violations, excessive 0s, errors in the CRC6 code words, framing bit errors, and number of multiframes that the device is out of receive synchronization. Each of these three counters are automatically updated on either 1-second boundaries (CCR3.2=0) or every 42 ms (CCR3.2=1) as determined by the timer in Status Register 2 (SR2.5). Hence, these registers contain performance data from either the previous second or the previous 42 ms. The user can use the interrupt from the 1-second timer to determine when to read these registers. The user has a full second (or 42 ms) to read the counters before the data is lost. All three counters will saturate at their respective maximum counts and they will not rollover (note: only the Line Code Violation Count Register has the potential to overflow but the bit error would have to exceed 10-2 before this would occur).
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5.1 Line Code Violation Count Register (LCVCR)
Line Code Violation Count Register 1 High (LCVCR1) is the most significant word and LCVCR2 is the least significant word of a 16-bit counter that records code violations (CVs). CVs are defined as Bipolar Violations (BPVs) or excessive 0s. See Table 5.1 for details of exactly what the LCVCRs count. If the B8ZS mode is set for the receive side via CCR2.2, then B8ZS code words are not counted. This counter is always enabled; it is not disabled during receive loss of synchronization (RLOS=1) conditions.
LCVCR1: LINE CODE VIOLATION COUNT REGISTER 1 (Address=23 Hex) LCVCR2: LINE CODE VIOLATION COUNT REGISTER 2 (Address=24 Hex)
(MSB) LCV15 LCV7 LCV14 LCV6 LCV13 LCV5 POSITION LCVCR1.7 LCVCR2.0 LCV12 LCV4 LCV11 LCV3 LCV10 LCV2 LCV9 LCV1 (LSB) LCV8 LCVCR1 LCV0 LCVCR2
SYMBOL LCV15 LCV0
NAME AND DESCRIPTION MSB of the 16-bit code violation count LSB of the 16-bit code violation count
LINE CODE VIOLATION COUNTING ARRANGEMENTS Table 5-1
COUNT EXCESSIVE 0S? (RCR1.7) no yes no yes B8ZS ENABLED? (CCR2.2) no no yes yes WHAT IS COUNTED IN THE LCVCRs BPVs BPVs + 16 consecutive 0s BPVs (B8ZS code words not counted) BPVs + 8 consecutive 0s
5.2 Path Code Violation Count Register (PCVCR)
When the receive side of the DS2152 is set to operate in the ESF framing mode (CCR2.3=1), PCVCR will automatically be set as a 12-bit counter that will record errors in the CRC6 code words. When set to operate in the D4 framing mode (CCR2.3=0), PCVCR will automatically count errors in the Ft framing bit position. Via the RCR2.1 bit, the DS2152 can be programmed to also report errors in the Fs framing bit position. The PCVCR will be disabled during receive loss of synchronization (RLOS=1) conditions. See Table 5-2 for a detailed description of exactly what errors the PCVCR counts.
PCVCR1: PATH VIOLATION COUNT REGISTER 1 (Address=25 Hex) PCVCR2: PATH VIOLATION COUNT REGISTER 2 (Address=26 Hex)
(MSB)
(note 1) CRC/FB7 (note 1) CRC/FB6 (note 1) CRC/FB5 (note 1) CRC/FB4 CRC/FB11 CRC/FB3 CRC/FB10 CRC/FB2 CRC/FB9 CRC/FB1
(LSB)
CRC/FB8 CRC/FB0 PCVCR1 PCVCR2
SYMBOL CRC/FB11
POSITION PCVCR1.3
NAME AND DESCRIPTION MSB of the 12-Bit CRC6 Error or Frame Bit Error Count (note #2) LSB of the 12-Bit CRC6 Error or Frame Bit Error Count (note #2) 39 of 93
CRC/FB0
PCVCR2.0
DS2152
NOTES:
1. The upper nibble of the counter at address 25 is used by the Multiframes Out of Sync Count Register. 2. PCVCR counts either errors in CRC code words (in the ESF framing mode; CCR2.3=1) or errors in the framing bit position (in the D4 framing mode; CCR2.3=0).
PATH CODE VIOLATION COUNTING ARRANGEMENTS Table 5-2
FRAMING MODE (CCR2.3) D4 D4 ESF COUNT Fs ERRORS? (RCR2.1) no yes don't care WHAT IS COUNTED IN THE PCVCRs errors in the Ft pattern errors in both the Ft & Fs patterns errors in the CRC6 code words
5.3 MULTIFRAMES OUT OF SYNC COUNT REGISTER (MOSCR)
Normally the MOSCR is used to count the number of multiframes that the receive synchronizer is out of sync (RCR2.0=1). This number is useful in ESF applications needing to measure the parameters Loss Of Frame Count (LOFC) and ESF Error Events as described in AT&T publication TR54016. When the MOSCR is operated in this mode, it is not disabled during receive loss of synchronization (RLOS=1) conditions. The MOSCR has alternate operating mode whereby it will count either errors in the Ft framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF mode). When the MOSCR is operated in this mode, it is disabled during receive loss of synchronization (RLOS=1) conditions. See Table 5-3 for a detailed description of what the MOSCR is capable of counting.
MOSCR1: MULTIFRAMES OUT OF SYNC COUNT REGISTER 1 (Address=25 Hex) MOSCR2: MULTIFRAMES OUT OF SYNC COUNT REGISTER 2 (Address=27 Hex)
(MSB)
MOS/FB11 MOS/FB7 MOS/FB10 MOS/FB6 MOS/FB9 MOS/FB5 MOS/FB8 MOS/FB4 (note 1) MOS/FB3 (note 1) MOS/FB2 (note 1) MOS/FB1
(LSB)
(note 1) MOS/FB0 MOSCR1 MOSCR2
SYMBOL MOS/FB11
POSITION MOSCR1.7
NAME AND DESCRIPTION MSB of the 12-Bit Multiframes Out of Sync or F-Bit Error Count (note #2) LSB of the 12-Bit Multiframes Out of Sync or F-Bit Error Count (note #2)
MOS/FB0
MOSCR2.0
NOTES:
1. The lower nibble of the counter at address 25 is used by the Path Code Violation Count Register. 2. MOSCR counts either errors in framing bit position (RCR2.0=0) or the number of multiframes out of sync (RCR2.0=1).
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MULTIFRAMES OUT OF SYNC COUNTING ARRANGEMENTS Table 5-3
FRAMING MODE (CCR2.3) D4 D4 ESF ESF COUNT MOS OR F-BIT ERRORS (RCR2.0) MOS F-Bit MOS F-Bit WHAT IS COUNTED IN THE MOSCRs number of multiframes out of sync errors in the Ft pattern number of multiframes out of sync errors in the FPS pattern
6.0 DS0 MONITORING FUNCTION
The DS2152 has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR5 register. In the receive direction, the RCM0 to RCM4 bits in the CCR6 register need to be properly set. The DS0 channel pointed to by the TCM0 to TCM4 bits will appear in the Transmit DS0 Monitor (TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the decimal decode of the appropriate T1 channel. For example, if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into CCR5 and CCR6: TCM4 = 0 RCM4 = 0 TCM3 = 0 RCM3 = 1 TCM2 = 1 RCM2 = 1 TCM1 = 0 RCM1 = 1 TCM0 = 1 RCM0 = 0
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CCR5: COMMON CONTROL REGISTER 5 (Address=19 Hex) [repeated here from section 3 for convenience]
(MSB) TJC LLB LIAIS POSITION CCR5.7 CCR5.6 CCR5.5 TCM4 TCM3 TCM2 TCM1 (LSB) TCM0
SYMBOL TJC LLB LIAIS
NAME AND DESCRIPTION Transmit Japanese CRC Enable. See Section 3 for details. Local Loopback. See Section 3 for details. Line Interface AIS Generation Enable. See Section 3 for details. Transmit Channel Monitor Bit 4. MSB of a channel decode that determines which transmit DS0 channel data will appear in the TDS0M register. Transmit Channel Monitor Bit 3. Transmit Channel Monitor Bit 2. Transmit Channel Monitor Bit 1. Transmit Channel Monitor Bit 0. LSB of the channel decode that determines which transmit DS0 channel data will appear in the TDS0M register.
TCM4
CCR5.4
TCM3 TCM2 TCM1 TCM0
CCR5.3 CCR5.2 CCR5.1 CCR5.0
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TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address=1A Hex)
(MSB) B1 B2 B3 POSITION TDS0M.7 B4 B5 B6 B7 (LSB) B8
SYMBOL B1
NAME AND DESCRIPTION Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first bit to be transmitted). Transmit DS0 Channel Bit 2. Transmit DS0 Channel Bit 3. Transmit DS0 Channel Bit 4. Transmit DS0 Channel Bit 5. Transmit DS0 Channel Bit 6. Transmit DS0 Channel Bit 7. Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last bit to be transmitted).
B2 B3 B4 B5 B6 B7 B8
TDS0M.6 TDS0M.5 TDS0M.4 TDS0M.3 TDS0M.2 TDS0M.1 TDS0M.0
CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex) [repeated here from section 3 for convenience]
(MSB) RJC POSITION CCR6.7 CCR6.6 CCR6.5 RCM4 RCM3 RCM2 RCM1 (LSB) RCM0
SYMBOL RJC -
NAME AND DESCRIPTION Receive Japanese CRC Enable. See Section 3 for details. Not Assigned. Should be set to 0 when written. Not Assigned. Should be set to 0 when written.
RCM4
CCR6.4
Receive Channel Monitor Bit 4. MSB of a channel decode that determines which receive DS0 channel data will appear in the RDS0M register. Receive Channel Monitor Bit 3. Receive Channel Monitor Bit 2. Receive Channel Monitor Bit 1. Receive Channel Monitor Bit 0. LSB of the channel decode that determines which receive DS0 channel data will appear in the RDS0M register. 43 of 93
RCM3 RCM2 RCM1 RCM0
CCR6.3 CCR6.2 CCR6.1 CCR6.0
DS2152
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RDS0M: RECEIVE DS0 MONITOR REGISTER (Address=1F Hex)
(MSB) B1 B2 B3 POSITION RDS0M.7 B4 B5 B6 B7 (LSB) B8
SYMBOL B1
NAME AND DESCRIPTION Receive DS0 Channel Bit 1. MSB of the DS0 channel (first bit to be received). Receive DS0 Channel Bit 2. Receive DS0 Channel Bit 3. Receive DS0 Channel Bit 4. Receive DS0 Channel Bit 5. Receive DS0 Channel Bit 6. Receive DS0 Channel Bit 7. Receive DS0 Channel Bit 8. LSB of the DS0 channel (last bit to be received).
B2 B3 B4 B5 B6 B7 B8
RDS0M.6 RDS0M.5 RDS0M.4 RDS0M.3 RDS0M.2 RDS0M.1 RDS0M.0
7.0 SIGNALING OPERATION
The DS2152 contains provisions for both processor based (i.e., software based) signaling bit access and for hardware based access. Both the processor based access and the hardware based access can be used simultaneously if necessary. The processor based signaling is covered in Section 7.1 and the hardware based signaling is covered in Section 7.2.
7.1 PROCESSOR BASED SIGNALING
The robbed-bit signaling bits embedded in the T1 stream can be extracted from the receive stream and inserted into the transmit stream by the DS2152. There is a set of 12 registers for the receive side (RS1 to RS12) and 12 registers on the transmit side (TS1 to TS12). The signaling registers are detailed below. The CCR1.5 bit is used to control the robbed signaling bits as they appear at RSER. If CCR1.5 is set to 0, then the robbed signaling bits will appear at the RSER pin in their proper position as they are received. If CCR1.5 is set to a 1, then the robbed signaling bit positions will be forced to a 1 at RSER. If hardware based signaling is being used, then CCR1.5 must be set to 0.
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RS1 TO RS12: RECEIVE SIGNALING REGISTERS (Address=60 to 6B Hex)
(MSB) A(8) A(16) A(24) B(8) B(16) B(24) A/C(8) A/C(16) A/C(24) B/D(8) B/D(16) B/D(24) A(7) A(15) A(23) B(7) B(15) B(23) A/C(7) A/C(15) A/C(23) B/D(7) B/D(15) B/D(23) A(6) A(14) A(22) B(6) B(14) B(22) A/C(6) A/C(14) A/C(22) B/D(6) B/D(14) B/D(22) POSITION RS12.7 RS1.0 A(5) A(13) A(21) B(5) B(13) B(21) A/C(5) A/C(13) A/C(21) B/D(5) B/D(13) B/D(21) A(4) A(12) A(20) B(4) B(12) B(20) A/C(4) A/C(12) A/C(20) B/D(4) B/D(12) B/D(20) A(3) A(11) A(19) B(3) B(11) B(19) A/C(3) A/C(11) A/C(19) B/D(3) B/D(11) B/D(19) A(2) A(10) A(18) B(2) B(10) B(18) A/C(2) A/C(10) A/C(18) B/D(2) B/D(10) B/D(18) (LSB) A(1) A(9) A(17) B(1) B(9) B(17) A/C(1) A/C(9) A/C(17) B/D(1) B/D(9) B/D(17) RS1 (60) RS2 (61) RS3 (62) RS4 (63) RS5 (64) RS6 (65) RS7 (66) RS8 (67) RS9 (68) RS10 (69) RS11 (6A) RS12 (6B)
SYMBOL D(24) A(1)
NAME AND DESCRIPTION Signaling Bit D in Channel 24 Signaling Bit A in Channel 1
Each Receive Signaling Register (RS1 to RS12) reports the incoming robbed-bit signaling from eight DS0 channels. In the ESF framing mode, there can be up to 4 signaling bits per channel (A, B, C, and D). In the D4 framing mode, there are only 2 signaling bits per channel (A and B). In the D4 framing mode, the DS2152 will replace the C and D signaling bit positions with the A and B signaling bits from the previous multiframe. Hence, whether the DS2152 is operated in either framing mode, the user needs only to retrieve the signaling bits every 3 ms. The bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can utilize the Receive Multiframe Interrupt in the Receive Status Register 2 (SR2.7) to know when to retrieve the signaling bits. The Receive Signaling Registers are frozen and not updated during a loss of sync condition (SR1.0=1). They will contain the most recent signaling information before the "OOF" occurred. The signaling data reported in RS1 to RS12 is also available at the RSIG and RSER pins. A change in the signaling bits from one multiframe to the next will cause the RSC status bit (SR2.0) to be set. The user can enable the INT pin to toggle low upon detection of a change in signaling by setting the IMR2.0 bit. Once a signaling change has been detected, the user has at least 2.75 ms to read the data out of the RS1 to RS12 registers before the data will be lost.
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TS1 TO TS12: TRANSMIT SIGNALING REGISTERS (Address=70 to 7B Hex)
(MSB) A(8) A(16) A(24) B(8) B(16) B(24) A/C(8) A/C(16) A/C(24) B/D(8) B/D(16) B/D(24) A(7) A(15) A(23) B(7) B(15) B(23) A/C(7) A/C(15) A/C(23) B/D(7) B/D(15) B/D(23) A(6) A(14) A(22) B(6) B(14) B(22) A/C(6) A/C(14) A/C(22) B/D(6) B/D(14) B/D(22) POSITION TS12.7 TS1.0 A(5) A(13) A(21) B(5) B(13) B(21) A/C(5) A/C(13) A/C(21) B/D(5) B/D(13) B/D(21) A(4) A(12) A(20) B(4) B(12) B(20) A/C(4) A/C(12) A/C(20) B/D(4) B/D(12) B/D(20) A(3) A(11) A(19) B(3) B(11) B(19) A/C(3) A/C(11) A/C(19) B/D(3) B/D(11) B/D(19) A(2) A(10) A(18) B(2) B(10) B(18) A/C(2) A/C(10) A/C(18) B/D(2) B/D(10) B/D(18) (LSB) A(1) A(9) A(17) B(1) B(9) B(17) A/C(1) A/C(9) A/C(17) B/D(1) B/D(9) B/D(17) TS1 (70) TS2 (71) TS3 (72) TS4 (73) TS5 (74) TS6 (75) TS7 (76) TS8 (77) TS9 (78) TS10 (79) TS11 (7A) TS12 (7B)
SYMBOL D(24) A(1)
NAME AND DESCRIPTION Signaling Bit A in Channel 24 Signaling Bit D in Channel 1
Each Transmit Signaling Register (TS1 to TS12) contains the robbed-bit signaling for eight DS0 channels that will be inserted into the outgoing stream if enabled to do so via TCR1.4. In the ESF framing mode, there can be up to 4 signaling bits per channel (A, B, C, and D). On multiframe boundaries, the DS2152 will load the values present in the Transmit Signaling Register into an outgoing signaling shift register that is internal to the device. The user can utilize the Transmit Multiframe Interrupt in Status Register 2 (SR2.6) to know when to update the signaling bits. In the ESF framing mode, the interrupt will come every 3 ms and the user has a full 3ms to update the TSRs. In the D4 framing mode, there are only 2 signaling bits per channel (A and B). However, in the D4 framing mode the DS2152 uses the C and D bit positions as the A and B bit positions for the next multiframe. The DS2152 will load the values in the TSRs into the outgoing shift register every other D4 multiframe.
7.2 HARDWARE BASED SIGNALING 7.2.1 Receive Side
In the receive side of the hardware based signaling, there are two operating modes for the signaling buffer: signaling extraction and signaling reinsertion. Signaling extraction involves pulling the signaling bits from the receive data stream and buffering them over a four multiframe buffer and outputting them in a serial PCM fashion on a channel-by-channel basis at the RSIG output. This mode is always enabled. In this mode, the receive elastic store may be enabled or disabled. If the receive elastic store is enabled, then the backplane clock (RSYSCLK) can be either 1.544 MHz or 2.048 MHz. In the ESF framing mode, the ABCD signaling bits are output on RSIG in the lower nibble of each channel. The RSIG data is updated once a multiframe (3 ms) unless a freeze is in effect. In the D4 framing mode, the AB signaling bits are output twice on RSIG in the lower nibble of each channel. Hence, bits 5 and 6 contain the same data as bits 7 and 8 respectively in each channel. The RSIG data is updated once a multiframe (1.5 ms) unless a freeze is in effect. See the timing diagrams in Section 15 for some examples. The other hardware based signaling operating mode called signaling reinsertion can be invoked by setting the RSRE control bit high (CCR4.7=1). In this mode, the user will provide a multiframe sync at the 47 of 93
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RSYNC pin and the signaling data will be re-aligned at the RSER output according to this applied multiframe boundary. In this mode, the elastic store must be enabled however the backplane clock can be either 1.544 MHz or 2.048 MHz. If the signaling reinsertion mode is enabled, the user can control which channels have signaling reinsertion performed on a channel-by-channel basis by setting the RPCSI control bit high (CCR4.6) and then programming the RCHBLK output pin to go high in the channels in which the signaling reinsertion should not occur. If the RPCSI bit is set low, then signaling reinsertion will occur in all channels when the signaling reinsertion mode is enabled (RSRE=1). How to control the operation of the RCHBLK output pin is covered in Section 9. In signaling reinsertion mode, the user has the option to replace all of the extracted robbed-bit signaling bit positions with 1s. This option is enabled via the RFSA1 control bit (CCR4.5) and it can be invoked on a per-channel basis by setting the RPCSI control bit (CCR4.6) high and then programming RCHBLK appropriately just like the per-channel signaling reinsertion operates. The signaling data in the four-multiframe buffer will be frozen in a known good state upon either a loss of synchronization (OOF event), carrier loss, or frame slip. This action meets the requirements of BellCore TR-TSY-000170 for signaling freezing. To allow this freeze action to occur, the RFE control bit (CCR4.4) should be set high. The user can force a freeze by setting the RFF control bit (CCR4.3) high. The RSIGF output pin provides a hardware indication that a freeze is in effect. The four-multiframe buffer provides a three-multiframe delay in the signaling bits provided at the RSIG pin (and at the RSER pin if RSRE=1). When freezing is enabled (RFE=1), the signaling data will be held in the last known good state until the corrupting error condition subsides. When the error condition subsides, the signaling data will be held in the old state for at least an additional 9 ms (or 4.5 ms in D4 framing mode) before being allowed to be updated with new signaling data.
7.2.2 Transmit Side
Via the THSE control bit (CCR4.2), the DS2152 can be set up to take the signaling data presented at the TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin. The user has the ability to control which channels are to have signaling data from the TSIG pin inserted into them on a channel-by-channel basis by setting the TPCSI control bit (CCR4.1) high. When TPCSI is enabled, channels in which the TCHBLK output has been programmed to be set high in, will not have signaling data from the TSIG pin inserted into them. The hardware signaling insertion capabilities of the DS2152 are available whether the transmit side elastic store is enabled or disabled. If the elastic store is enabled, the backplane clock (TSYSCLK) can be either 1.544 MHz or 2.048 MHz.
8.0 PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK
The DS2152 can replace data on a channel-by-channel basis in both the transmit and receive directions. The transmit direction is from the backplane to the T1 line and is covered in Section 8.1. The receive direction is from the T1 line to the backplane and is covered in Section 8.2.
8.1 TRANSMIT SIDE CODE GENERATION
In the transmit direction there are two methods by which channel data from the backplane can be overwritten with data generated by the DS2152. The first method which is covered in Section 8.1.1 was a feature contained in the original DS2151 while the second method, which is covered in Section 8.1.2, is a new feature of the DS2152.
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8.1.1 Simple Idle Code Insertion and Per-Channel Loopback
The first method involves using the Transmit Idle Registers (TIR1/2/3) to determine which of the 24 T1 channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR). This method allows the same 8-bit code to be placed into any of the 24 T1 channels. If this method is used, then the CCR4.0 control bit must be set to 0. Each of the bit positions in the Transmit Idle Registers (TIR1/TIR2/TIR3) represents a DS0 channel in the outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code contained in the Transmit Idle Definition Register (TIDR). Robbed-bit signaling and Bit 7 stuffing will occur over the programmed Idle Code unless the DS0 channel is made transparent by the Transmit Transparency Registers. The Transmit Idle Registers (TIRs) have an alternate function that allows them to define a Per-Channel Loop-Back (PCLB). If the TIRFS control bit (CCR4.0) is set to 1, then the TIRs will determine which channels (if any) from the backplane should be replaced with the data from the receive side or, in other words, off of the T1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to TSYNC.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address=3C to 3E Hex) [Also used for Per-Channel Loopback]
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 POSITION TIR3.7 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 CH9 CH17 TIR1 (3C) TIR2 (3D) TIR3 (3E)
SYMBOL CH24
NAME AND DESCRIPTION Transmit Idle Registers. 0=do not insert the Idle Code in the TIDR into this channel 1=insert the Idle Code in the TIDR into this channel
CH1
TIR1.0
NOTE:
If CCR4.0=1, then a 0 in the TIRs implies that channel data is to be sourced from TSER and a 1 implies that channel data is to be sourced from the output of the receive side framer (i.e., Per-Channel Loopback; see Figure 1-1).
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=3F Hex)
(MSB) TIDR7 TIDR6 TIDR5 POSITION TIDR.7 TIDR.0 TIDR4 TIDR3 TIDR2 TIDR1 (LSB) TIDR0
SYMBOL TIDR7 TIDR0
NAME AND DESCRIPTION MSB of the Idle Code (this bit is transmitted first) LSB of the Idle Code (this bit is transmitted last)
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8.1.2 Per-Channel Code Insertion
The second method involves using the Transmit Channel Control Registers (TCC1/2/3) to determine which of the 24 T1 channels should be overwritten with the code placed in the Transmit Channel Registers (TC1 to TC24). This method is more flexible than the first in that it allows a different 8-bit code to be placed into each of the 24 T1 channels.
TC1 TO TC24: TRANSMIT CHANNEL REGISTERS (Address=40 to 4F and 50 to 57 Hex) (for brevity, only channel 1 is shown; see Table 1-3 for other register address)
(MSB) C7 C6 C5 POSITION TC1.7 TC1.0 C4 C3 C2 C1 (LSB) C0 TC1 (50)
SYMBOL C7 C0
NAME AND DESCRIPTION MSB of the Code (this bit is transmitted first) LSB of the Code (this bit is transmitted last)
TCC1/TCC2/TCC3: TRANSMIT CHANNEL CONTROL REGISTER (Address=16 to 18 Hex)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 POSITION TCC3.7 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 CH9 CH17 TCC1 (16) TCC2 (17) TCC3 (18)
SYMBOL CH24
NAME AND DESCRIPTION Transmit Channel 24 Code Insertion Control Bit 0=do not insert data from the TC1 register into the transmit data stream 1 = insert data from the TC1 register into the transmit data stream Transmit Channel 1 Code Insertion Control Bit 0=do not insert data from the TC32 register into the transmit data stream 1 = insert data from the TC32 register into the transmit data stream
CH1
TCC1.0
8.2 RECEIVE SIDE CODE GENERATION
In the receive direction there are also two methods by which channel data to the backplane can be overwritten with data generated by the DS2152. The first method which is covered in Section 8.2.1 was a feature contained in the original DS2151 while the second method which is covered in Section 8.2.2 is a new feature of the DS2152.
8.2.1 Simple Code Insertion
The first method on the receive side involves using the Receive Mark Registers (RMR1/2/3) to determine which of the 24 T1 channels should be overwritten with either a 7Fh idle code or with a digital milliwatt 50 of 93
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pattern. The RCR2.7 bit will determine which code is used. The digital milliwatt code is an 8-byte repeating pattern that represents a 1 kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the RMRs represents a particular channel. If a bit is set to a 1, then the receive data in that channel will be replaced with one of the two codes. If a bit is set to 0, no replacement occurs.
RMR1/RMR2/RMR3: RECEIVE MARK REGISTERS (Address=2D to 2F Hex)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 POSITION RMR3.7 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 RMR1(2D) CH9 RMR2(2E) CH17 RMR3(2F)
SYMBOL CH24
NAME AND DESCRIPTION Receive MARK Registers. 0=do not affect the receive data associated with this channel 1=replace the receive data associated with this channel with either the idle code or the digital milliwatt code (depends on the RCR2.7 bit)
CH1
RMR1.0
8.2.2 Per-Channel Code Insertion
The second method involves using the Receive Channel Control Registers (RCC1/2/3) to determine which of the 24 T1 channels off of the T1 line and going to the backplane should be overwritten with the code placed in the Receive Channel Registers (RC1 to RC24). This method is more flexible than the first in that it allows a different 8-bit code to be placed into each of the 24 T1 channels.
RC1 TO RC24: RECEIVE CHANNEL REGISTERS (Address=58 to 5F and 80 to 8F Hex) (for brevity, only channel 1 is shown; see Table 1-3 for other register address)
(MSB) C7 C6 C5 POSITION RC1.7 RC1.0 C4 C3 C2 C1 (LSB) C0 RC1 (58)
SYMBOL C7 C0
NAME AND DESCRIPTION MSB of the Code (this bit is sent first to the backplane) LSB of the Code (this bit is sent last to the backplane)
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RCC1/RCC2/RCC3: RECEIVE CHANNEL CONTROL REGISTER (Address=1B to 1D Hex)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 POSITION RCC3.7 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 RCC1 (1B) CH9 RCC2 (1C) CH17 RCC3 (1D)
SYMBOL CH24
NAME AND DESCRIPTION Receive Channel 24 Code Insertion Control Bit 0=do not insert data from the RC24 register into the receive data stream 1=insert data from the RC24 register into the receive data stream Receive Channel 1 Code Insertion Control Bit 0=do not insert data from the RC1 register into the receive data stream 1=insert data from the RC1 register into the receive data stream
CH1
RCC1.0
9.0 CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively. The RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in Fractional T1 or ISDN-PRI applications. When the appropriate bits are set to a 1, the RCHBLK and TCHCLK pins will be held high during the entire corresponding channel time. See the timing in Section 15 for an example.
RCBR1/RCBR2/RCBR3: RECEIVE CHANNEL BLOCKING REGISTERS (Address=6C to 6E Hex)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 POSITION RCBR3.7 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 RCBR1 (6C) CH9 RCBR2 (6D) CH17 RCBR3 (6E)
SYMBOL CH24
NAME AND DESCRIPTION Receive Channel Blocking Registers. 0=force the RCHBLK pin to remain low during this channel time 1=force the RCHBLK pin high during this channel time
CH1
RCBR1.0
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TCBR1/TCBR2/TCBR3: TRANSMIT CHANNEL BLOCKING REGISTERS (Address=32 to 34 Hex)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 POSITION TCBR3.7 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 TCBR1 (32) CH9 TCBR1 (33) CH17 TCBR1 (34)
SYMBOL CH24
NAME AND DESCRIPTION Transmit Channel Blocking Registers. 0=force the TCHBLK pin to remain low during this channel time 1=force the TCHBLK pin high during this channel time
CH1
TCBR1.0
10.0 ELASTIC STORES OPERATION
The DS2152 contains dual two-frame (386 bits) elastic stores, one for the receive direction and one for the transmit direction. These elastic stores have two main purposes. First, they can be used to rate convert the T1 data stream to 2.048 Mbps (or a multiple of 2.048 Mbps), which is the E1 rate. Secondly, they can be used to absorb the differences in frequency and phase between the T1 data stream and an asynchronous (i.e., not frequency locked) backplane clock (which can be 1.544 MHz or 2.048 MHz). The backplane clock can burst at rates up to 8.192 MHz. Both elastic stores contain fully controlled slip capability, which is necessary for this second purpose. The receive side elastic store can be enabled via CCR1.2 and the transmit side elastic store is enabled via CCR1.7. The elastic stores can be forced to a known depth via the Elastic Store Reset bit (CCR3.6). Toggling the CCR3.6 bit forces the read and write pointers into opposite frames. Both elastic stores within the DS2152 are fully independent and no restrictions apply to the sourcing of the various clocks that are applied to them. The transmit side elastic store can be enabled whether the receive elastic store is enabled or disabled and vice versa. Also, each elastic store can interface to either a 1.544 MHz or 2.048 MHz backplane without regard to the backplane rate the other elastic store is interfacing.
10.1 RECEIVE SIDE
If the receive side elastic store is enabled (CCR1.2=1), then the user must provide either a 1.544 MHz (CCR1.3=0) or 2.048 MHz (CCR1.3=1) clock at the RSYSCLK pin. The user has the option of either providing a frame/multiframe sync at the RSYNC pin (RCR2.3=1) or having the RSYNC pin provide a pulse on frame boundaries (RCR2.3=0). If the user wishes to obtain pulses at the frame boundary, then RCR2.4 must be set to 0; if the user wishes to have pulses occur at the multiframe boundary, then RCR2.4 must be set to 1. The DS2152 will always indicate frame boundaries via the RFSYNC output whether the elastic store is enabled or not. If the elastic store is enabled, then multiframe boundaries will be indicated via the RMSYNC output. If the user selects to apply a 2.048 MHz clock to the RSYSCLK pin, then the data output at RSER will be forced to all 1s every fourth channel and the F-bit will be placed in the MSB bit position of channel 1. Hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be forced to a 1. Also, in 2.048 MHz applications, the RCHBLK output will be forced high during the same channels as the RSER pin. See Section 15 for more details. This is useful in T1 to CEPT (E1) conversion applications. If the 386-bit elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of data (193 bits) will be repeated at RSER and the SR1.4 and RIR1.3 bits will be set to a 1 except the MSB of channel 1. See Figure 15-5. If the buffer fills, then a full frame of data will be deleted and the SR1.4 and RIR1.4 bits will be set to a 1.
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10.2 TRANSMIT SIDE
The operation of the transmit elastic store is very similar to the receive side. The transmit side elastic store is enabled via CCR1.7. A 1.544 MHz (CCR1.4=0) or 2.048 MHz (CCR1.4=1) clock can be applied to the TSYSCLK input. If the user selects to apply a 2.048 MHz clock to the TSYSCLK pin, then the data input at TSER will be ignored every fourth channel. Hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be ignored. The F-bit may be sampled at the MSB of channel 1. See Figure 15-10. The user must supply an 8 kHz frame sync pulse to the TSSYNC input. Also, in 2.048 MHz applications the TCHBLK output will be forced high during the channels ignored by the DS2152. See Section 15 for more details. Controlled slips in the transmit elastic store are reported in the RIR2.3 bit, and the direction of the slip is reported in the RIR2.5 and RIR2.4 bits.
10.3 MINIMUM DELAY SYNCHRONOUS RSYSCLK/TSYSCLK MODE
In applications where the DS2152 is connected to backplanes that are frequency-locked to the recovered T1 clock (i.e., the RCLK output), the full two-frame depth of the onboard elastic stores is really not needed. In fact, in some delay-sensitive applications the normal two-frame depth may be excessive. If the CCR3.7 bit is set to 1, then the receive elastic store (and also the transmit elastic store if it is enabled) will be forced to a maximum depth of 32 bits instead of the normal 386 bits. In this mode, RSYSCLK and TSYSCLK must be tied together and they must be frequency-locked to RCLK. All of the slip contention logic in the DS2152 is disabled (since slips cannot occur). Also, since the buffer depth is no longer two frames deep, the DS2152 must be set up to source a frame pulse at the RSYNC pin and this output must be tied to the TSSYNC input. On power-up after the RSYSCLK and TSYSCLK signals have locked to the RCLK signal, the elastic store reset bit (CCR3.6) should be toggled from a 0 to a 1 to insure proper operation.
11.0 FDL/Fs EXTRACTION AND INSERTION
The DS2152 has the ability to extract/insert data from/into the Facility Data Link (FDL) in the ESF framing mode and from/into Fs-bit position in the D4 framing mode. Since SLC-96 utilizes the Fs-bit position, this capability can also be used in SLC-96 applications. The DS2152 contains a complete HDLC and BOC controller for the FDL and this operation is covered in Section 11.1. To allow for backward compatibility between the DS2152 and earlier devices, the DS2152 maintains some legacy functionality for the FDL and this is covered in Section 11.2. Section 11.3 covers D4 and SLC-96 operation. Please contact the factory for a copy of C language source code for implementing the FDL on the DS2152.
11.1 HDLC AND BOC CONTROLLER FOR THE FDL 11.1.1 General Overview
The DS2152 contains a complete HDLC controller with 16-byte buffers in both the transmit and receive directions as well as separate dedicated hardware for Bit Oriented Codes (BOC). The HDLC controller performs all the necessary overhead for generating and receiving Performance Report Messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC controller automatically generates and detects flags, generates and checks the CRC check sum, generates and detects abort sequences, stuffs and destuffs 0s (for transparency), and byte-aligns to the FDL data stream. The 16-byte buffers in the HDLC controller are large enough to allow a full PRM to be received or transmitted without host intervention. The BOC controller will automatically detect incoming BOC sequences and alert the host. When the BOC ceases, the DS2152 will also alert the host. The user can set the device up to send any of the possible 6-bit BOC codes.
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There are nine registers that the host will use to operate and control the operation of the HDLC and BOC controllers. A brief description of the registers is shown in Table 11-1.
HDLC/BOC CONTROLLER REGISTER LIST Table 11-1
NAME FDL Control Register (FDLC) FDL Status Register (FDLS) FDL Interrupt Mask Register (FIMR) Receive PRM Register (RPRM) Receive BOC Register (RBOC) Receive FDL FIFO Register (RFFR) Transmit PRM Register (TPRM) Transmit BOC Register (TBOC) Transmit FDL FIFO Register (TFFR) FUNCTION general control over the HDLC and BOC controllers key status information for both transmit and receive directions allows/stops status bits to/from causing an interrupt status information on receive HDLC controller status information on receive BOC controller access to 16-byte HDLC FIFO in receive direction status information on transmit HDLC controller enables/disables transmission of BOC codes access to 16-byte HDLC FIFO in transmit direction
11.1.2 Status Register for the FDL
Four of the HDLC/BOC controller registers (FDLS, RPRM, RBOC, and TPRM) provide status information. When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers will be set to a 1. Some of the bits in these four FDL status registers are latched and some are real-time bits that are not latched. Section 11.1.4 contains register descriptions that list which bits are latched and which are not. With the latched bits, when an event occurs and a bit is set to a 1, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again. The real-time bits report the current instantaneous conditions that are occurring, and the history of these bits is not latched. Like the other status registers in the DS2152, the user will always proceed a read of any of the four registers with a write. The byte written to the register will inform the DS2152 which of the latched bits the user wishes to read and have cleared (the real-time bits are not affected by writing to the status register). The user will write a byte to one of these registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit location, the read register will be updated with current value and it will be cleared. When a 0 is written to a bit position, the read register will not be updated and the previous value will be held. A write to the status and information registers will be immediately followed by a read of the same register. The read result should be logically AND'ed with the mask byte that was just written and this value should be written back into the same register to insure that bit does indeed clear. This second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. This write-read-write (for polled driven access) or write-read (for interruptdriven access) scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS2152 with higher-order software languages.
Like the SR1 and SR2 status registers, the FDLS register has the unique ability to initiate a hardware interrupt via the INT output pin. Each of the events in the FDLS can be either masked or unmasked from the interrupt pin via the FDL Interrupt Mask Register (FIMR). Interrupts will force the INT pin low when the event occurs. The INT pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.
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11.1.3 Basic Operation Details
To allow the DS2152 to properly source/receive data from/to the HDLC and BOC controller the legacy FDL circuitry (which is described in Section 11.2) should be disabled and the following bits should be programmed as shown: TCR1.2 = 1 (source FDL data from the HDLC and BOC controller) TBOC.6 = 1 (enable HDLC and BOC controller) CCR2.5 = 0 (disable SLC-96 and D4 Fs-bit insertion) CCR2.4 = 0 (disable legacy FDL 0 stuffer) CCR2.1 = 0 (disable SLC-96 reception) CCR2.0 = 0 (disable legacy FDL 0 stuffer) IMR2.4 = 0 (disable legacy receive FDL buffer full interrupt) IMR2.3 = 0 (disable legacy transmit FDL buffer empty interrupt) IMR2.2 = 0 (disable legacy FDL match interrupt) IMR2.1 = 0 (disable legacy FDL abort interrupt) As a basic guideline for interpreting and sending both HDLC messages and BOC messages, the following sequences can be applied:
Receive a HDLC Message or a BOC
1. enable RBOC and RPS interrupts 2. wait for interrupt to occur 3. if RBOC=1, then follow steps 5 and 6 4. if RPS=1, then follow steps 7 thru 12 5. if LBD=1, a BOC is present, then read the code from the RBOC register and take action as needed 6. if BD=0, a BOC has ceased, take action as needed and then return to step 1 7. disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt 8. read RPRM to obtain REMPTY status a. if REMPTY=0, then record OBYTE, CBYTE, and POK bits and then read the FIFO a1. if CBYTE=0 then skip to step 9 a2. if CBYTE=1 then skip to step 11 b. if REMPTY=1, then skip to step 10 9. repeat step 8 10. wait for interrupt, skip to step 8 11. if POK=0, then discard whole packet, if POK=1, accept the packet 12. disable RPE, RNE, or RHALF interrupt, enable RPS interrupt and return to step 1
Transmit a HDLC Message
1. make sure HDLC controller is finished sending any previous messages and is currently sending flags by checking that the FIFO is empty by reading the TEMPTY status bit in the TPRM register 2. enable either the THALF or TNF interrupt 3. read TPRM to obtain TFULL status a. if TFULL=0, then write a byte into the FIFO and skip to next step (special case occurs when the last byte is to be written, in this case set TEOM=1 before writing the byte and then skip to step 6) b. if TFULL=1, then skip to step 5 56 of 93
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4. repeat step 3 5. wait for interrupt, skip to step 3 6. disable THALF or TNF interrupt and enable TMEND interrupt 7. wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
Transmit a BOC
1. write 6-bit code into TBOC 2. set SBOC bit in TBOC=1
11.1.4 HDLC/BOC Register Description FDLC: FDL CONTROL REGISTER (Address=00 Hex)
(MSB) RBR RHR TFS POSITION FDLC.7 THR TABT TEOM TZSD (LSB) TCRCF
SYMBOL RBR
NAME AND DESCRIPTION Receive BOC Reset. A 0 to 1 transition will reset the BOC circuitry. Must be cleared and set again for a subsequent reset. Receive HDLC Reset. A 0 to 1 transition will reset the HDLC controller. Must be cleared and set again for a subsequent reset. Transmit Flag/Idle Select. 0 = 7Eh 1 = FFh Transmit HDLC Reset. A 0 to 1 transition will reset both the HDLC controller and the transmit BOC circuitry. Must be cleared and set again for a subsequent reset. Transmit Abort. A 0 to 1 transition will cause the FIFO contents to be dumped and one FEh abort to be sent followed by 7Eh or FFh flags/idle until a new packet is initiated by writing new data into the FIFO. Must be cleared and set again for a subsequent abort to be sent. Transmit End of Message. Should be set to a 1 just before the last data byte of a HDLC packet is written into the transmit FIFO at TFFR. This bit will be cleared by the HDLC controller when the last byte has been transmitted. Transmit 0 Stuffer Defeat. Overrides internal enable. 0 = enable the 0 stuffer (normal operation) 1 = disable the 0 stuffer Transmit CRC Defeat. 0 = enable CRC generation (normal operation) 1 = disable CRC generation 57 of 93
RHR
FDLC.6
TFS
FDLC.5
THR
FDLC.4
TABT
FDLC.3
TEOM
FDLC.2
TZSD
FDLC.1
TCRCD
FDLC.0
DS2152
FDLS: FDL STATUS REGISTER (Address=01 Hex)
(MSB) RBOC RPE RPS POSITION FDLS.7 RHALF RNE THALF TNF (LSB) TMEND
SYMBOL RBOC
NAME AND DESCRIPTION Receive BOC Detector Change of State. Set whenever the BOC detector sees a change of state from a BOC Detected to a No Valid Code seen or vice versa. The setting of this bit prompt the user to read the RBOC register for details. Receive Packet End. Set when the HDLC controller detects either the finish of a valid message (i.e., CRC check complete) or when the controller has experienced a message fault such as a CRC checking error, or an overrun condition, or an abort has been seen. The setting of this bit prompts the user to read the RPRM register for details. Receive Packet Start. Set when the HDLC controller detects an opening byte. The setting of this bit prompts the user to read the RPRM register for details. Receive FIFO Half Full. Set when the receive 16-byte FIFO fills beyond the halfway point. The setting of this bit prompts the user to read the RPRM register for details. Receive FIFO Not Empty. Set when the receive 16-byte FIFO has at least 1 byte available for a read. The setting of this bit prompts the user to read the RPRM register for details. Transmit FIFO Half Empty. Set when the transmit 16-byte FIFO empties beyond the halfway point. The setting of this bit prompts the user to read the TPRM register for details. Transmit FIFO Not Full. Set when the transmit 16-byte FIFO has at least 1 byte available. The setting of this bit prompts the user to read the TPRM register for details. Transmit Message End. Set when the transmit HDLC controller has finished sending a message. The setting of this bit prompts the user to read the TPRM register for details.
RPE
FDLS.6
RPS
FDLS.5
RHALF
FDLS.4
RNE
FDLS.3
THALF
FDLS.2
TNF
FDLS.1
TMEND
FDLS.0
NOTE:
The RBOC, RPE, RPS, and TMEND bits are latched and will be cleared when read.
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FIMR: FDL INTERRUPT MASK REGISTER (Address=02 Hex)
(MSB) RBOC RPE RPS POSITION FIMR.7 RHALF RNE THALF TNF (LSB) TMEND
SYMBOL RBOC
NAME AND DESCRIPTION Receive BOC Detector Change of State. 0 = interrupt masked 1 = interrupt enabled Receive Packet End. 0 = interrupt masked 1 = interrupt enabled Receive Packet Start. 0 = interrupt masked 1 = interrupt enabled Receive FIFO Half Full. 0 = interrupt masked 1 = interrupt enabled Receive FIFO Not Empty. 0 = interrupt masked 1 = interrupt enabled Transmit FIFO Half Empty. 0 = interrupt masked 1 = interrupt enabled Transmit FIFO Not Full. 0 = interrupt masked 1 = interrupt enabled Transmit Message End. 0 = interrupt masked 1 = interrupt enabled
RPE
FIMR.6
RPS
FIMR.5
RHALF
FIMR.4
RNE
FIMR.3
THALF
FIMR.2
TNF
FIMR.1
TMEND
FIMR.0
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RPRM: RECEIVE RPM REGISTER (Address=03 Hex)
(MSB) RABT RCRCE ROVR POSITION RPRM.7 RVM REMPTY POK CBYTE (LSB) OBYTE
SYMBOL RABT
NAME AND DESCRIPTION Abort Sequence Detected. Set whenever the HDLC controller sees 7 or more 1s in a row. CRC Error. Set when the CRC checksum is in error. Overrun. Set when the HDLC controller has attempted to write a byte into an already full receive FIFO. Valid Message. Set when the HDLC controller has detected and checked a complete HDLC packet. Empty. A real-time bit that is set high when the receive FIFO is empty. Packet OK. Set when the byte available for reading in the receive FIFO at RFDL is the last byte of a valid message (and hence no abort was seen, no overrun occurred, and the CRC was correct). Closing Byte. Set when the byte available for reading in the receive FIFO at RFDL is the last byte of a message (whether the message was valid or not). Opening Byte. Set when the byte available for reading in the receive FIFO at RFDL is the first byte of a message.
RCRCE ROVR
RPRM.6 RPRM.5
RVM
RPRM.4
REMPTY
RPRM.3
POK
RPRM.2
CBYTE
RPRM.1
OBYTE
RPRM.0
NOTE:
The RABT, RCRCE, ROVR, and RVM bits are latched and will be cleared when read.
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RBOC: RECEIVE BOC REGISTER (Address=04 Hex)
(MSB) LBD BD BOC5 POSITION RBOC.7 BOC4 BOC3 BOC2 BOC1 (LSB) BOC0
SYMBOL LBD
NAME AND DESCRIPTION Latched BOC Detected. A latched version of the BD status bit (RBOC.6). Will be cleared when read. BOC Detected. A real-time bit that is set high when the BOC detector is presently seeing a valid sequence and set low when no BOC is currently being detected. BOC Bit 5. Last bit received of the 6-bit codeword. BOC Bit 4. BOC Bit 3. BOC Bit 2. BOC Bit 1. BOC Bit 0. First bit received of the 6-bit codeword.
BD
RBOC.6
BOC5 BOC4 BOC3 BOC2 BOC1 BOC0
RBOC.5 RBOC.4 RBOC.3 RBOC.2 RBOC.1 RBOC.0
NOTE:
1. The LBD bit is latched and will be cleared when read. 2. The RBOC0 to RBOC5 bits display the last valid BOC code verified; these bits will be set to all 1s on reset.
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RFFR: RECEIVE FDL FIFO REGISTER (Address=05 Hex)
(MSB) FDL7 FDL6 FDL5 POSITION RFFR.7 RFFR.6 RFFR.5 RFFR.4 RFFR.3 RFFR.2 RFFR.1 RFFR.0 FDL4 FDL3 FDL2 FDL1 (LSB) FDL0
SYMBOL FDL7 FDL6 FDL5 FDL4 FDL3 FDL2 FDL1 FDL0
NAME AND DESCRIPTION FDL Data Bit 7. MSB of a HDLC packet data byte. FDL Data Bit 6. FDL Data Bit 5. FDL Data Bit 4. FDL Data Bit 3. FDL Data Bit 2. FDL Data Bit 1. FDL Data Bit 0. LSB of a HDLC packet data byte.
TPRM: TRANSMIT PRM REGISTER (Address=06 Hex)
(MSB) POSITION TPRM.7 TPRM.6 TPRM.5 TPRM.4 TPRM.3 TPRM.2 TEMPTY TFULL (LSB) UDR
SYMBOL TEMPTY
NAME AND DESCRIPTION Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Transmit FIFO Empty. A real-time bit that is set high when the FIFO is empty. Transmit FIFO Full. A real-time bit that is set high when the FIFO is full. Underrun. Set when the transmit FIFO unwantedly empties out and an abort is automatically sent.
TFULL
TPRM.1
UDR
TPRM.0
NOTE:
The UDR bit is latched and will be cleared when read. 62 of 93
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TBOC: TRANSMIT BOC REGISTER (Address=07 Hex)
(MSB) SBOC HBEN BOC5 POSITION TBOC.7 BOC4 BOC3 BOC2 BOC1 (LSB) BOC0
SYMBOL SBOC
NAME AND DESCRIPTION Send BOC. Rising edge triggered. Must be transitioned from a 0 to a 1 transmit the BOC code placed in the BOC0 to BOC5 bits instead of data from the HDLC controller. Transmit HDLC & BOC Controller Enable. 0 = source FDL data from the TLINK pin 1 = source FDL data from the onboard HDLC and BOC controller BOC Bit 5. Last bit transmitted of the 6-bit codeword. BOC Bit 4. BOC Bit 3. BOC Bit 2. BOC Bit 1. BOC Bit 0. First bit transmitted of the 6-bit codeword.
HBEN
TBOC.6
BOC5 BOC4 BOC3 BOC2 BOC1 BOC0
TBOC.5 TBOC.4 TBOC.3 TBOC.2 TBOC.1 TBOC.0
TFFR: TRANSMIT FDL FIFO REGISTER (Address=08 Hex)
(MSB) FDL7 FDL6 FDL5 POSITION TFFR.7 TFFR.6 TFFR.5 TFFR.4 TFFR.3 TFFR.2 TFFR.1 TFFR.0 FDL4 FDL3 FDL2 FDL1 (LSB) FDL0
SYMBOL FDL7 FDL6 FDL5 FDL4 FDL3 FDL2 FDL1 FDL0
NAME AND DESCRIPTION FDL Data Bit 7. MSB of a HDLC packet data byte. FDL Data Bit 6. FDL Data Bit 5. FDL Data Bit 4. FDL Data Bit 3. FDL Data Bit 2. FDL Data Bit 1. FDL Data Bit 0. LSB of a HDLC packet data byte.
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11.2 LEGACY FDL SUPPORT 11.2.1 Overview
In order to provide backward compatibility to the older DS2151 device, the DS2152 maintains the circuitry that existed in the previous generation of T1 Single-Chip Transceivers. Section 11.2 covers the circuitry and operation of this legacy functionality. In new applications, it is recommended that the HDLC controller and BOC controller described in Section 11.1 be used. On the receive side, it is possible to have both the new HDLC/BOC controller and the legacy hardware working at the same time. However, this is not possible on the transmit side since their can be only one source the of the FDL data internal to the device.
11.2.2 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2 ms (8 times 250 us). The DS2152 will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via IMR2.4, the INT pin will toggle low indicating that the buffer has filled and needs to be read. The user has 2 ms to read this data before it is lost. If the byte in the RFDL matches either of the bytes programmed into the RFDLM1 or RFDLM2 registers, then the SR2.2 bit will be set to a 1 and the INT pin will toggled low if enabled via IMR2.2. This feature allows an external microcontroller to ignore the FDL or Fs pattern until an important event occurs. The DS2152 also contains a 0 destuffer which is controlled via the CCR2.0 bit. In both ANSI T1.403 and TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states that no more than five 1s should be transmitted in a row so that the data does not resemble an opening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS2152 will automatically look for five 1s in a row, followed by a 0. If it finds such a pattern, it will automatically remove the 0. If the 0 destuffer sees six or more 1s in a row followed by a 0, the 0 is not removed. The CCR2.0 bit should always be set to a 1 when the DS2152 is extracting the FDL. More on how to use the DS2152 in FDL applications in this legacy support mode is covered in a separate Application Note.
RFDL: RECEIVE FDL REGISTER (Address=28 Hex)
(MSB) RFDL7 RFDL6 RFDL5 POSITION RFDL.7 RFDL.0 RFDL4 RFDL3 RFDL2 RFDL1 (LSB) RFDL0
SYMBOL RFDL7 RFDL0
NAME AND DESCRIPTION MSB of the Received FDL Code LSB of the Received FDL Code
The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs bits. The LSB is received first.
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RFDLM1: RECEIVE FDL MATCH REGISTER 1 (Address=29 Hex) RFDLM2: RECEIVE FDL MATCH REGISTER 2 (Address=2A Hex)
(MSB) RFDL7 RFDL6 RFDL5 POSITION RFDL.7 RFDL.0 RFDL4 RFDL3 RFDL2 RFDL1 (LSB) RFDL0
SYMBOL RFDL7 RFDL0
NAME AND DESCRIPTION MSB of the FDL Match Code LSB of the FDL Match Code
When the byte in the Receive FDL Register matches either of the two Receive FDL Match Registers (RFDLM1/RFDLM2), RSR2.2 will be set to a 1 and the INT will go active if enabled via IMR2.2.
11.2.3 Transmit Section
The transmit section will shift out into the T1 data stream either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL). When a new value is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing T1 data stream. After the full 8 bits have been shifted out, the DS2152 will signal the host microcontroller that the buffer is empty and that more data is needed by setting the SR2.3 bit to a 1. The INT will also toggle low if enabled via IMR2.3. The user has 2 ms to update the TFDL with a new value. If the TFDL is not updated, the old value in the TFDL will be transmitted once again. The DS2152 also contains a 0 stuffer which is controlled via the CCR2.4 bit. In both ANSI T1.403 and TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states that no more than five 1s should be transmitted in a row so that the data does not resemble an opening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.4, the DS2152 will automatically look for five 1s in a row. If it finds such a pattern, it will automatically insert a 0 after the five 1s. The CCR2.0 bit should always be set to a 1 when the DS2152 is inserting the FDL. More on how to use the DS2152 in FDL applications is covered in a separate Application Note.
TFDL: TRANSMIT FDL REGISTER (Address=7E Hex) [also used to insert Fs framing pattern in D4 framing mode; see Section 11.3]
(MSB) TFDL7 TFDL6 TFDL5 POSITION TFDL.7 TFDL.0 TFDL4 TFDL3 TFDL2 TFDL1 (LSB) TFDL0
SYMBOL TFDL7 TFDL0
NAME AND DESCRIPTION MSB of the FDL code to be transmitted LSB of the FDL code to be transmitted
The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first.
11.3 D4/SLC-96 OPERATION
In the D4 framing mode, the DS2152 uses the TFDL register to insert the Fs framing pattern. To allow the device to properly insert the Fs framing pattern, the TFDL register at address 7Eh must be programmed to 1Ch and the following bits must be programmed as shown: 65 of 93
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TCR1.2=0 (source Fs data from the TFDL register) CCR2.5=1 (allow the TFDL register to load on multiframe boundaries) Since the SLC-96 message fields share the Fs-bit position, the user can access these message fields via the TFDL and RFDL registers. Please see the separate Application Note for a detailed description of how to implement an SLC-96 function.
12.0 PROGRAMMABLE IN-BAND CODE GENERATION AND DETECTION
The DS2152 has the ability to generate and detect a repeating bit pattern that is from 1 to 8 bits in length. To transmit a pattern, the user will load the pattern to be sent into the Transmit Code Definition (TCD) register and select the proper length of the pattern by setting the TC0 and TC1 bits in the In-Band Code Control (IBCC) register. Once this is accomplished, the pattern will be transmitted as long as the TLOOP control bit (CCR3.1) is enabled. Normally (unless the transmit formatter is programmed to not insert the F-bit position) the DS2152 will overwrite the repeating pattern once every 193 bits to allow the F-bit position to be sent. See Figure 15-11 for more details. As an example, if the user wished to transmit the standard "loop up" code for Channel Service Units which is a repeating pattern of ...10000100001... then 80h would be loaded into TDR and the length would set to 5 bits. The DS2152 can detect two separate repeating patterns to allow for both a "loop up" code and a "loop down" code to be detected. The user will program the codes to be detected in the Receive Up Code Definition (RUPCD) register and the Receive Down Code Definition (RDNCD) register and the length of each pattern will be selected via the IBCC register. The DS2152 will detect repeating pattern codes in both framed and unframed circumstances with bit error rates as high as 10**-2. The code detector has a nominal integration period of 48 ms. Hence, after about 48 ms of receiving either code, the proper status bit (LUP at SR1.7 and LDN at SR1.6) will be set to a 1. Normally codes are sent for a period of 5 seconds. It is recommend that the software poll the DS2152 every 100 ms to 1000 ms until 5 seconds has elapsed to insure that the code is continuously present.
IBCC: IN-BAND CODE CONTROL REGISTER (Address=12 Hex)
(MSB) TC1 TC0 RUP2 POSITION IBCC.7 IBCC.6 IBCC.5 IBCC.4 IBCC.3 IBCC.2 IBCC.1 IBCC.0 RUP1 RUP0 RDN2 RDN1 (LSB) RDN0
SYMBOL TC1 TC0 RUP2 RUP1 RUP0 RDN2 RDN1 RDN0
NAME AND DESCRIPTION Transmit Code Length Definition Bit 1. See Table 12-1 Transmit Code Length Definition Bit 0. See Table 12-1 Receive Up Code Length Definition Bit 2. See Table 12-2 Receive Up Code Length Definition Bit 1. See Table 12-2 Receive Up Code Length Definition Bit 0. See Table 12-2 Receive Down Code Length Definition Bit 2. See Table 12-2 Receive Down Code Length Definition Bit 1. See Table 12-2 Receive Down Code Length Definition Bit 0. See Table 12-2 66 of 93
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TRANSMIT CODE LENGTH Table 12-1
TC1 0 0 1 1 TC0 0 1 0 1 LENGTH SELECTED 5 bits 6 bits / 3 bits 7 bits 8 bits / 4 bits / 2 bits / 1 bits
RECEIVE CODE LENGTH Table 12-2
RUP2/ RDN2 0 0 0 0 1 1 1 1 RUP1/ RDN1 0 0 1 1 0 0 1 1 RUP0/ RDN0 0 1 0 1 0 1 0 1 LENGTH SELECTED 1 bits 2 bits 3 bits 4 bits 5 bits 6 bits 7 bits 8 bits
TCD: TRANSMIT CODE DEFINITION REGISTER (Address=13 Hex)
(MSB) C7 C6 C5 POSITION TCD.7 C4 C3 C2 C1 (LSB) C0
SYMBOL C7
NAME AND DESCRIPTION Transmit Code Definition Bit 7. First bit of the repeating pattern. Transmit Code Definition Bit 6. Transmit Code Definition Bit 5. Transmit Code Definition Bit 4. Transmit Code Definition Bit 3. Transmit Code Definition Bit 2. A Don't Care if a 5-bit length is selected. Transmit Code Definition Bit 1. A Don't Care if a 5 or 6-bit length is selected. Transmit Code Definition Bit 0. A Don't Care if a 5, 6 or 7-bit length is selected.
C6 C5 C4 C3 C2
TCD.6 TCD.5 TCD.4 TCD.3 TCD.2
C1
TCD.1
C0
TCD.0
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RUPCD: RECEIVE UP CODE DEFINITION REGISTER (Address=14 Hex)
(MSB) C7 C6 C5 POSITION RUPCD.7 C4 C3 C2 C1 (LSB) C0
SYMBOL C7
NAME AND DESCRIPTION Receive Up Code Definition Bit 7. First bit of the repeating pattern. Receive Up Code Definition Bit 6. A Don't Care if a 1-bit length is selected. Receive Up Code Definition Bit 5. A Don't Care if a 1 or 2-bit length is selected. Receive Up Code Definition Bit 4. A Don't Care if a 1 to 3-bit length is selected. Receive Up Code Definition Bit 3. A Don't Care if a 1 to 4-bit length is selected. Receive Up Code Definition Bit 2. A Don't Care if a 1 to 5-bit length is selected. Receive Up Code Definition Bit 1. A Don't Care if a 1 to 6-bit length is selected. Receive Up Code Definition Bit 0. A Don't Care if a 1 to 7-bit length is selected.
C6
RUPCD.6
C5
RUPCD.5
C4
RUPCD.4
C3
RUPCD.3
C2
RUPCD.2
C1
RUPCD.1
C0
RUPCD.0
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RDNCD: RECEIVE DOWN CODE DEFINITION REGISTER (Address=15 Hex)
(MSB) C7 C6 C5 POSITION RDNCD.7 C4 C3 C2 C1 (LSB) C0
SYMBOL C7
NAME AND DESCRIPTION Receive Down Code Definition Bit 7. First bit of the repeating pattern. Receive Down Code Definition Bit 6. A Don't Care if a 1-bit length is selected. Receive Down Code Definition Bit 5. A Don't Care if a 1 or 2bit length is selected. Receive Down Code Definition Bit 4. A Don't Care if a 1 to 3bit length is selected. Receive Down Code Definition Bit 3. A Don't Care if a 1 to 4bit length is selected. Receive Down Code Definition Bit 2. A Don't Care if a 1 to 5bit length is selected. Receive Down Code Definition Bit 1. A Don't Care if a 1 to 6bit length is selected. Receive Down Code Definition Bit 0. A Don't Care if a 1 to 7bit length is selected.
C6
RDNCD.6
C5
RDNCD.5
C4
RDNCD.4
C3
RDNCD.3
C2
RDNCD.2
C1
RDNCD.1
C0
RDNCD.0
13.0 TRANSMIT TRANSPARENCY
Each of the 24 T1 channels in the transmit direction of the DS2152 can be either forced to be transparent or, in other words, can be forced to stop Bit 7 Stuffing and/or Robbed Signaling from overwriting the data in the channels. Transparency can be invoked on a channel by channel basis by properly setting the TTR1, TTR2, and TTR3 registers.
TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTER (Address=39 to 3B Hex)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 POSITION TTR3.7 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 TTR1 (39) CH9 TTR2 (3A) CH17 TTR3 (3B)
SYMBOL CH24
NAME AND DESCRIPTION Transmit Transparency Registers. 0=this DS0 channel is not transparent 1=this DS0 channel is transparent
CH1
TTR1.0
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Each of the bit positions in the Transmit Transparency Registers (TTR1/TTR2/TTR3) represent a DS0 channel in the outgoing frame. When these bits are set to a 1, the corresponding channel is transparent (or clear). If a DS0 is programmed to be clear, no robbed-bit signaling will be inserted nor will the channel have Bit 7 stuffing performed. However, in the D4 framing mode, bit 2 will be overwritten by a 0 when a Yellow Alarm is transmitted. Also, the user has the option to prevent the TTR registers from determining which channels are to have Bit 7 stuffing performed. If the TCR2.0 and TCR1.3 bits are set to 1, then all 24 T1 channels will have Bit 7 stuffing performed on them regardless of how the TTR registers are programmed. In this manner, the TTR registers are only affecting which channels are to have robbed-bit signaling inserted into them. Please see Figure 15-11 for more details.
14.0 LINE INTERFACE FUNCTION
The line interface function in the DS2152 contains three sections; (1) the receiver which handles clock and data recovery, (2) the transmitter which waveshapes and drives the T1 line, and (3) the jitter attenuator. Each of these three sections is controlled by the Line Interface Control Register (LICR), which is described below.
LICR: LINE INTERFACE CONTROL REGISTER (Address=7C Hex)
(MSB) L2 L1 L0 POSITION LICR.7 LICR.6 LICR.5 LICR.4 EGL JAS JABDS DJA (LSB) TPD LICR
SYMBOL L2 L1 L0 EGL
NAME AND DESCRIPTION Line Build Out Select Bit 2. Sets the transmitter build out; see the Table 14-2 Line Build Out Select Bit 1. Sets the transmitter build out; see the Table 14-2 Line Build Out Select Bit 0. Sets the transmitter build out; see the Table 14-2 Receive Equalizer Gain Limit. 0 = -36 dB 1 = -30 dB Jitter Attenuator Select. 0 = place the jitter attenuator on the receive side 1 = place the jitter attenuator on the transmit side Jitter Attenuator Buffer Depth Select 0 = 128 bits 1 = 32 bits (use for delay sensitive applications) Disable Jitter Attenuator. 0 = jitter attenuator enabled 1 = jitter attenuator disabled Transmit Power Down. 0 = normal transmitter operation 1 = powers down the transmitter and 3-states the TTIP and TRING pins
JAS
LICR.3
JABDS
LICR.2
DJA
LICR.1
TPD
LICR.0
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14.1 RECEIVE CLOCK AND DATA RECOVERY
The DS2152 contains a digital clock recovery system. See the DS2152 Block Diagram in Section 1 and Figure 14-1 for more details. The DS2152 couples to the receive T1 twisted pair via a 1:1 transformer. See Table 14-3 for transformer details. The 1.544 MHz clock attached at the MCLK pin is internally multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16 times oversampler which is used to recover the clock and data. This oversampling technique offers outstanding jitter tolerance (see Figure 14-2). Normally, the clock that is output at the RCLKO pin is the recovered clock from the T1 AMI/B8ZS waveform presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING, a Receive Carrier Loss (LRCL) condition will occur and the RCLKO will be sourced from the clock applied at the MCLK pin. If the jitter attenuator is either placed in the transmit path or is disabled, the RCLKO output can exhibit slightly shorter high cycles of the clock. This is due to the highly oversampled digital clock recovery circuitry. If the jitter attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores the RCLK to being close to 50% duty cycle. Please see the Receive AC Timing Characteristics in Section 16 for more details.
14.2 TRANSMIT WAVESHAPING AND LINE DRIVING
The DS2152 uses a set of laser-trimmed delay lines along with a precision Digital-to-Analog Converter (DAC) to create the waveforms that are transmitted onto the T1 line. The waveforms created by the DS2152 meet the latest ANSI, AT&T, and ITU specifications. See Figure 14-3. The user will select which waveform is to be generated by properly programming the L2/L1/L0 bits in the Line Interface Control Register (LICR). The DS2152 can set up in a number of various configurations depending on the application. See Table 14-2 and Figure 14-1.
LINE BUILD OUT SELECT IN LICR Table 14-2
L2 0 0 0 0 1 1 1 1 L1 0 0 1 1 0 0 1 1 L0 0 1 0 1 0 1 0 1 LINE BUILD OUT 0 to 133 feet / 0dB 133 to 266 feet 266 to 399 feet 399 to 533 feet 533 to 655 feet -7.5 dB -15 dB -22.5 dB APPLICATION DSX-1 / CSU DSX-1 DSX-1 DSX-1 DSX-1 CSU CSU CSU
Due to the nature of the design of the transmitter in the DS2152, very little jitter (less then 0.005 UIpp broadband from 10 Hz to 100 kHz) is added to the jitter present on TCLKI. Also, the waveforms that they create are independent of the duty cycle of TCLK. The transmitter in the DS2152 couples to the T1 transmit twisted pair via a 1:1.15 or 1:1.36 step up transformer as shown in Figure 14-1. In order for the devices to create the proper waveforms, this transformer used must meet the specifications listed in Table 14-3.
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TRANSFORMER SPECIFICATIONS Table 14-3
SPECIFICATION Turns Ratio Primary Inductance Leakage Inductance Intertwining Capacitance DC Resistance RECOMMENDED VALUE 1:1 (receive) and 1:1.15 or 1:1.36 (transmit) 5% 600 uH minimum 1.0 uH maximum 40 pF maximum 1.2 ohms maximum
14.3 JITTER ATTENUATOR
The DS2152 contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications. The characteristics of the attenuation are shown in Figure 14-4. The jitter attenuator can be placed in either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR. Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR. In order for the jitter attenuator to operate properly, a 1.544 MHz clock (50 ppm) must be applied at the MCLK pin or a crystal with similar characteristics must be applied across the MCLK and XTALD pins. If a crystal is applied across the MCLK and XTALD pins, then capacitors should be placed from each leg of the crystal to the local ground plane as shown in Figure 14-1. Onboard circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the TCLKI pin to create a smooth jitter free clock which is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLKI pin if the jitter attenuator is placed on the transmit side. If the incoming jitter exceeds either 120 UIpp (buffer depth is 128 bits) or 28 UIpp (buffer depth is 32 bits), then the DS2152 will divide the internal nominal 24.704 MHz clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. When the device divides by either 15 or 17, it also sets the Jitter Attenuator Limit Trip (JALT) bit in the Receive Information Register (RIR3.5).
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DS2152 EXTERNAL ANALOG CONNECTIONS Figure 14-1
NOTES:
1. Resistor values are 1%. 2. The Rt resistors are used to protect the device from over-voltage. 3. See the Separate Application Note for details on how to construct a protected interface. 4. Either a crystal can be applied across the MCLK and XTALD pins or a TTL level clock can be applied to just MCLK. 5. C1 and C2 should be 5 pF lower than 2 times the nominal loading capacitance of the crystal to adjust for the input capacitance of the DS2152.
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DS2152 JITTER TOLERANCE Figure 14-2
DS2152 TRANSMIT WAVEFORM TEMPLATE Figure 14-3
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DS2152 JITTER ATTENUATION Figure 14-4
15.0 TIMING DIAGRAMS RECEIVE SIDE D4 TIMING Figure 15-1
NOTES:
1. RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is not enabled (RCR2.5=0). 2. RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is enabled (RCR2.5=1). 3. RSYNC in the multiframe mode (RCR2.4=1). 4. RLINK data (Fs bits) is updated 1 bit prior to even frames and held for two frames. 5. RLINK and RLCLK are not synchronous with RSYNC when the receive side elastic store is enabled.
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RECEIVE SIDE BOUNDARY TIMING (WITH ELASTIC STORE DISABLED) Figure 15-2
NOTES:
1. RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is not enabled (RCR2.5=0). 2. RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is enabled (RCR2.5=1). 3. RSYNC in the multiframe mode (RCR2.4=1). 4. ZBTSI mode disabled (RCR2.6=0). 5. RLINK data (FDL bits) is updated 1 bit-time before odd frames and held for two frames. 6. ZBTSI mode is enabled (RCR2.6=1). 7. RLINK data (Z bits) is updated 1 bit-time before odd frames and held for four frames. 8. RLINK and RLCLK are not synchronous with RSYNC when the receive side elastic store is enabled.
RECEIVE SIDE BOUNDARY TIMING (WITH ELASTIC STORE DISABLED) Figure 15-3
NOTES:
1. RCHBLK is programmed to block channel 24. 2. Shown is RLINK/RLCLK in the ESF framing mode.
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RECEIVE SIDE 1.544 MHz BOUNDARY TIMING (WITH ELASTIC STORE ENABLED) Figure 15-4
NOTES:
1. RSYNC is in the output mode (RCR2.3=0). 2. RSYNC is in the input mode (RCR2.3=1). 3. RCHBLK is programmed to block channel 24.
RECEIVE SIDE 2.048 MHz BOUNDARY TIMING (WITH ELASTIC STORE ENABLED) Figure 15-5
NOTES:
1. RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to 1. 2. RSYNC is in the output mode (RCR2.3=0). 3. RSYNC is in the input mode (RCR2.3=1). 4. RCHBLK is forced to 1 in the same channels as RSER (see Note 1). 5. The F-bit position is passed through the receive side elastic store. 6. RCHCLK does not transition high in the channels in which the RSER data is forced to 1 (see note 1).
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TRANSMIT SIDE D4 TIMING Figure 15-6
NOTES:
1. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is not enabled (TCR2.4=0). 2. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is enabled (TCR2.4=1). 3. TSYNC in the multiframe mode (TCR2.3=1). 4. TLINK data (Fs bits) is sampled during the F-bit position of even frames for insertion into the outgoing T1 stream when enabled via TCR1.2. 5. TLINK and TLCLK are not synchronous with TSSYNC.
TRANSMIT SIDE TIMING Figure 15-7
NOTES:
1. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is not enabled (TCR2.4=0). 2. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is enabled (TCR2.4=1). 3. TSYNC in the multiframe mode (TCR2.3=1). 4. ZBTSI mode disabled (TCR2.5=0). 5. TLINK data (FDL bits) is sampled during the F-bit time of odd frame and inserted into the outgoing T1 stream if enabled via TCR1.2. 6. ZBTSI mode is enabled (TCR2.5=1). 7. TLINK data (Z bits) is sampled during the F-bit time of frames 1, 5, 9, 13, 17, and 21 and inserted into the outgoing stream if enabled via TCR1.2. 8. TLINK and TLCLK are not synchronous with TSSYNC.
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TRANSMIT SIDE BOUNDARY TIMING Figure 15-8
NOTES:
1. TSYNC is in the output mode (TCR2.2=1). 2. TSYNC is in the input mode (TCR2.2=0). 3. TCHBLK is programmed to block channel 2. 4. Shown is TLINK/TLCLK in the ESF framing mode.
TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING (WITH ELASTIC STORE ENABLED) Figure 15-9
NOTES:
1. TCHBLK is programmed to block channel 24 (if the TPCSI bit is set, then the signaling data at TSIG will be ignored during channel 24).
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TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING (WITH ELASTIC STORE ENABLED) Figure 15-10
NOTES:
1. TSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored. 2. TCHBLK is programmed to block channel 31 (if the TPCSI bit is set, then the signaling data at TSIG will be ignored). 3. TCHBLK is forced to 1 in the same channels where TSER is ignored (see Note 1). 4. The F-bit position for the T1 frame is sampled and passed through the transmit side elastic store (normally the transmit side formatter overwrites the F-bit position unless the formatter is programmed to pass-through the F-bit position). 5. TCHCLK does not transition high in the channel in which the data at TSER is ignored (see note 1).
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DS2152 TRANSMIT DATA FLOW Figure 15-11
NOTE:
1. TCLK should be tied to RCLK and TSYNC should be tied to RFSYNC for data to be properly sourced from RSER.
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ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature for DS2152L Operating Temperature for DS2152LN Storage Temperature Soldering Temperature * -1.0V to +7.0V 0C to 70C -40C to +85C -55C to +125C 260C for 10 seconds
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Logic 1 Logic 0 Supply SYMBOL VIH VIL VDD MIN 2.0 -0.3 4.75
(0C to 70C for DS2152L; -40C to +85C for DS2152LN)
TYP MAX VDD+0.3 +0.8 5.25 UNITS V V V NOTES
1
CAPACITANCE
PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP 5 7 MAX
(tA=25C)
UNITS pF pF NOTES
DC CHARACTERISTICS
PARAMETER Supply Current @ 5V Input Leakage Output Leakage Output Current (2.4V) Output Current (0.4V)
(0C to 70C; VDD=5V 5% for DS2152L; -40C to +85C; VDD=5V 5% for DS2152LN)
SYMBOL IDD IIL ILO IOH IOL MIN -1.0 -1.0 +4.0 TYP 75 MAX +1.0 1.0 UNITS mA A A mA mA NOTES 2 3 4
NOTES:
1. Applies to RVDD, TVDD, and DVDD. 2. TCLK=RCLK=TSYSCLK=RSYSCLK=1.544 MHz; outputs open circuited. 3. 0.0V < VIN < VDD. 4. Applied to INT when 3-stated.
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AC CHARACTERISTICS MULTIPLEXED PARALLEL PORT (MUX=1)
PARAMETER Cycle Time Pulse Width, DS Low or RD High Pulse Width, DS High or RD Low Input Rise/Fall Times R/ W Hold Time R/ W Setup Time Before DS High CS Setup Time Before DS, WR or RD active CS Hold Time Read Data Hold Time Write Data Hold Time Muxed Address Valid to AS or ALE Fall Muxed Address Hold Time Delay Time, DS, WR or RD to AS or ALE Rise Pulse Width AS or ALE High Delay Time, AS or ALE to DS, WR or RD Output Data Delay Time from DS or RD Data Setup Time (see Figures 16-1 to 16-3 for details)
(0C to 70C; VDD=5V 5% for DS2152L; -40C to +85C; VDD=5V 5% for DS2152LN)
SYMBOL tCYC PWEL PWEH t R , tF tRWH tRWS tCS tCH tDHR tDHW tASL tAHL tASD PWASH tASED tDDR tDSW MIN 200 100 100 10 50 20 0 10 0 15 10 20 30 10 20 50 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES
20
50
80
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AC CHARACTERISTICS RECEIVE SIDE
PARAMETER RCLKO Period RCLKO Pulse Width RCLKO Pulse Width RCLKI Period RCLKI Pulse Width RSYSCLK Period RSYSCLK Pulse Width RSYNC Set Up to RSYSCLK Falling RSYNC Pulse Width RPOSI/RNEGI Set UP to RCLKI Falling RPOSI/RNEGI Hold From RCLKI Falling RSYSCLK/RCLKI Rise and Fall Times Delay RCLKO to RPOSO, RNEGO Valid Delay RCLK to RSER, RDATA, RSIG, RLINK Valid Delay RCLK to RCHCLK, RSYNC, RCHBLK, RFSYNC, RLCLK Delay RSYSCLK to RSER, RSIG Valid Delay RSYSCLK to RCHCLK, RCHBLK, RMSYNC, RSYNC See Figures 16-4 to 16-6 for details.
(0C to 70C; VDD=5V 5% for DS2152L; (-40C to +85C; VDD=5V 5% for DS2152LN)
SYMBOL MIN tLP 250 tLH 250 tLL 200 tLH 200 tCL tCP 75 tCH 75 tCL 122 tSP 122 tSP 50 tSH 50 tSL tSU 20 tPW 50 tSU 20 tHD 20 t R , tF tDD tD1 tD2 tD3 tD4 TYP 648 324 324 324 324 648 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 1 1 2 2
648 488
3 4
tSH-5
25 50 50 50 50 50
NOTES:
1. Jitter attenuator enabled in the receive path. 2. Jitter attenuator disabled or enabled in the transmit path. 3. RSYSCLK=1.544 MHz 4. RSYSCLK=2.048 MHz
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AC CHARACTERISTICS TRANSMIT SIDE
PARAMETER TCLK Period TCLK Pulse Width TCLKI Period TCLKI Pulse Width TSYSCLK Period TSYSCLK Pulse Width TSYNC or TSSYNC Set Up to TCLK or TSYSCLK Falling TSYNC or TSSYNC Pulse Width TSER, TSIG, TDATA, TLINK, TPOSI, TNEGI Set Up to TCLK, TSYSCLK, TCLKI Falling TSER, TSIG, TDATA, TLINK, TPOSI, TNEGI Hold from TCLK, TSYSCLK, TCLKI Falling TCLK, TCLKI, or TSYSCLK Rise and Fall Times Delay TCLKO to TPOSO, TNEGO Valid Delay TCLK to TESO Valid Delay TCLK to TCHBLK, TCHBLK, TSYNC, TLCLK Delay TSYSCLK to TCHCLK, TCHBLK See Figures 16-7 to 16-9 for details.
(0C to 70C; VDD=5V 5% for DS2152L; -40C to +85C; VDD=5V 5% for DS2152LN)
SYMBOL tCP tCH tCL tLP tLH tLL tSP tSP tSH tSL tSU tPW tSU MIN 75 75 648 75 75 122 122 50 50 20 50 20 TYP 648 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns NOTES
648 448
1 2
tCH-5 or tSH-5
tHD
20
ns
t R , tF tDD tD1 tD2 tD3
25 50 50 50 75
ns ns ns ns ns
NOTES:
1. TSYSCLK=1.544 MHz. 2. TSYSCLK=2.048 MHz.
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AC CHARACTERISTICS NON-MULTIPLEXED PARALLEL (0C to 70C; VDD=5V 5% for DS2152L; PORT (MUX=0) -40C to +85C; VDD=5V 5% for DS2152LN)
PARAMETER SYMBOL t1 Set Up Time for A0 to A7 Valid to CS Active t2 Set Up Time for CS Active to either RD , WR , or DS Active t3 Delay Time from either RD or DS Active to Data Valid t4 Hold Time from either RD , WR , or DS Inactive to CS Inactive t5 Hold Time from CS Inactive to Data Bus 3-state t6 Wait Time from either WR or DS Active to Latch Data t7 Data Set Up Time to either WR or DS Inactive t8 Data Hold Time to either WR or DS Inactive t9 Address Hold from either WR or DS Inactive See Figures 16-10 to 16-13 for details. MIN 0 0 75 0 5 75 10 0 10 20 TYP MAX UNITS ns ns ns ns ns ns ns ns ns NOTES
INTEL BUS READ AC TIMING (BTS=0/MUX=1) Figure 16-1
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INTEL BUS WRITE AC TIMING (BTS=0/MUX=1) Figure 16-2
MOTOROLA BUS AC TIMING (BTS=1/MUX=1) Figure 16-3
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RECEIVE SIDE AC TIMING Figure 16-4
NOTES:
1. RSYNC is in the output mode (RCR2.3=0). 2. Shown is RLINK/RLCLK in the ESF framing mode. 3. No relationship between RCHCLK and RCHBLK and the other signals is implied.
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RECEIVE SYSTEM SIDE AC TIMING Figure 16-5
NOTES:
1. RSYNC is in the output mode (RCR2.3=0). 2. RSYNC is in the input mode (RCR2.3=1).
RECEIVE LINE INTERFACE AC TIMING Figure 16-6
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TRANSMIT SIDE AC TIMING Figure 16-7
NOTES:
1. TSYNC is in the output mode (TCR2.2=1). 2. TSYNC is in the input mode (TCR2.2=0). 3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled. 4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled. 5. TLINK is only sampled during F-bit locations. 6. No relationship between TCHCLK and TCHBLK and the other signals is implied.
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TRANSMIT SYSTEM SIDE AC TIMING Figure 16-8
NOTES:
1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. 2. TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic store is enabled.
TRANSMIT LINE INTERFACE SIDE AC TIMING Figure 16-9
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INTEL BUS READ AC TIMING (BTS=0/MUX=0) Figure 16-10
INTEL BUS WRITE AC TIMING (BTS=0/MUX=0) Figure 16-11
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MOTOROLA BUS READ AC TIMING (BTS=1/MUX=0) Figure 16-12
MOTOROLA BUS WRITE AC TIMING (BTS=1/MUX=0) Figure 16-13
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DS2152 100-PIN LQFP
PKG DIM A A1 A2 b C D D1 E E1 e L
100-PIN MIN MAX 1.60 0.05 1.35 1.45 0.17 0.27 0.09 0.20 15.80 16.20 14.00 BSC 15.80 16.20 14.00 BSC 0.50 BSC 0.45 0.75
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